SIPI Engineer

Responsibilities:
Responsible for Signal Integrity and Power Integrity simulations at feasibility, pre-layout, and post-layout phases of product design.
Responsible for coordinating with the HW design team, layout team, NPI, and manufacturing vendors to resolve SI/stackup-related issues.
Responsible for providing SI/PI constraints document/guidelines to the layout team.
Responsible for end-to-end channel simulations for multi-gigabit serial links like 32/64/112/224 Gbps.
Responsible for SIPI simulations of HBM/DDR6/5 LPDDR6/5 LPCAM, DIMMs; PCIe Gen 5/6/7 and other high speed buses.
Work with multiple teams distributed globally.
Responsible for characterizing the various interfaces in the product and verifying the simulations against measurements.
Responsible for preparing and implementing SIPI checklists for various stages of product development.
Requirements:
Bachelor's or master's degree in electrical/electronics engineering or PhD in the signal/power integrity field.
Good-to-Have:
10+ years of relevant SI/PI simulation and characterization experience with BS/MS or 5 years with PhD.
Deep knowledge in using SI, PI tools: Ansys HFSS/SIwave, Allegro Sigrity SI/PI, ADS, HyperLynx, and HSPICE tools.
Excellent hands-on experience in simulation of PCIe Gen4/5/6 multi-gigabit serial buses of 28/32/56/112Gbps and higher, high-speed memory buses DDRx/LPDDRx, etc.
Hands-on experience in electrical/design validation/compliance testing using high-speed scopes, TDR/VNA, and other instruments.
Excellent written and oral communication skills.

Experience
10-14 yrs