STA/Timing and Physical Design Engineer (Senior/Lead) - Modem Team

Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > Hardware Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Experience: 2–6 Years from product based companies
Education: B.E/M.E in ECE, EE, VLSI, Microelectronics, or related fields with strong academic credentials.
Job Summary
Seeking a highly motivated STA/Timing Engineer to drive timing analysis and closure for advanced Modem SoCs. The candidate will work closely with RTL, Physical Design, DFT, and CAD teams to achieve timing signoff across advanced technology nodes. Having Physical Design experience and candidate looking for PD and STA combined ownership can apply.
Key Responsibilities
Perform block/full Modem STA and timing closure across MMMC scenarios.
Drive setup/hold closure, ECO implementation, and timing signoff.
Analyze timing at each Netlist to GDS stage
Collaborate with RTL, PD, and DFT teams to resolve timing issues.
Analyze noise, crosstalk, OCV/AOCV impacts and optimize critical paths.
Validate timing constraints (SDC).
Automate timing flows using Tcl/Perl/Python scripts.
Required Skills
Strong hands-on experience in STA, Timing Closure, MMMC, SDC, ECO.
Expertise in Synopsys PrimeTime/PTPX and Cadence Tempus
Good understanding of Digital Design, Synthesis, Physical Design, CTS, and Routing.
Scripting skills in Tcl/Perl/Python.
Experience with advanced technology nodes is preferred.
Having Physical Design experience and candidate looking for PD and STA combined ownership can apply
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Work arrangement
No