Physical Design Engineer

Key Skills Required :
• Strong experience in Constraint Development.
• Hands-on experience with Static Timing Analysis (STA).
• Experience in:
o Pre-layout and Post-layout STA checks
o Check Timing
o No Clock checks
o Constraint endpoint checks
o Constraint validation and analysis
• PrimeTime is the preferred STA tool.
• Exposure to LEC/Formality is a plus but not mandatory.
Important Note
• The requirement is focused on Constraint Development and STA validation activities.
• Candidates with timing analysis expertise are preferred over profiles that are primarily focused on PnR activities.
• Timing closure experience can be an added advantage; however, it is not the primary requirement.
Experience Criteria
• The requested experience range is 6 to 9 years.
• However, We can look for 5+ years of experience if they possess strong hands-on expertise in STA and constraint development.
● Good to have (secondary) skills: ● Timing CDC crossing understanding
• Conformal or Netlist based ECO implementation
● AMD knowledge will really help in current project
● Soft Skills • Strong communication skills and able to interact with different cross functional teams
● Education Background B.Tech / M.Tech in Electronics, VLSI or related field
Job Description
We are looking for an experienced STA Engineers to join our team in Hyderabad. In this role, you will learn and contribute to implementation activities like timing constraints, STA, logical equivalence check etc. You will get hands-on exposure to industry standard tools and methodologies while working alongside experienced engineers.
Job Responsibilities / Day-to-Day Activities :
• Should be able to develop constraints for different timing modes like Functional, Scan shift etc
• Able to do static timing checks like check timing, update timing and able debug issues in this
• Should be able to debug Formality/Conformal logical equivalence check (LEC)
Qualifications & Experiences:
• B.E/B.Tech/M.Tech in Electronics, VLSI or related field.
• Strong understanding of digital logic design and timing constraints & STA.
• Understanding of Verilog
• Familiartiy with EDA tools and scripting

Work arrangement
No