Staff Engineer, Physical Design

Company Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.
Job Description
Renesas India is seeking an experienced Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with strong cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.
Key Responsibilities
Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solution.
Qualifications
6+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs
Strong expertise in:
Timing closure and constraint management
Congestion analysis and resolution
Power integrity and power-aware physical implementation
Block and subsystem-level physical design flows
Solid understanding of SoC-level floorplanning and clocking methodologies, including:
Clock domain partitioning
Clock tree architecture
Skew management
Clock gating (Candidate is expected to collaborate effectively at the SoC level, not lead these activities.)
BTech or MTech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field
Hands-on experience with industry-standard tools such as:
Synopsys ICC2, Fusion Compiler, PrimeTime
Cadence Innovus, Tempus, Certus
Signoff and analysis platforms
Proficiency in scripting and automation using Tcl, Python, and/or Perl
Deep knowledge of end-to-end SoC design flows, with strong collaboration experience across timing, power, clocking, verification, and backend teams
Strong understanding of low-power design techniques and power-aware implementation methodologies
Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Work arrangement
No