Sr. Substrates Development and Ramp Engineer

Job Details:
Job Description: Supports management/senior leadership to incorporate process and quality improvements in Intel's supply chain strategy. Defines material inspection methodology, conducts studies related to cost control, process control, and production yield, and implements plans and programs to optimize supply chain. Supports product long range plan development by defining next generation methodology capabilities to support Intel's supply chain roadmap. Explores and benchmarks emerging technology in the industry. Contributes to Intel's future technology definition and requirements. Highlights gaps between roadmap strategy, manufacturing capability, and market demands and recommends solutions to addresses those gaps. Tracks supply demand trends, conducts root cause analysis to find opportunities for process and quality improvements, and collaborates with supply chain leads to implement solutions. Leads supplier selections for new business in partnership with commodity managers and technical/quality partners and drives product and purchase specification content to ensure commodity performance compliance. Performs alternate sourcing risk mitigation for single sourced commodities. Establishes control standards, determines KPIs, monitors performance against targets, and drives root cause analysis for supply chain issues to arrive at solutions. Drives supplier process window validation activities on critical process modules through all stages of development. Drives supplier improvements on quality, reliability, yield, and cost. Maintains quality standards and systems, creating relevant specifications to minimize variability and subjectivity to align with operational capability requirements. Leads quality excursion management and drives failure mode analysis with suppliers.
Qualifications:BS, MS, or PhD in Science or Engineering fields with minimum 8 years experiences in Semiconductor Fab, Substrates or Mother Boards or Assembly Test development or manufacturing environment is required.
In-depth knowledge required in Semiconductor Fab, Substrate or Mother Boards or Assembly Test manufacturing process,.
Process development and optimization, manufacturing operations management, Analytical Problem Solving, Statistical Process Control (SPC)
Knowledge, hand-on skills and experience in quality management, data analytics, raw materials management, cleanroom operations, foreign material control and supplier management will be a very strong added advantage.
Fluent communication and articulation skills in business level English, strong presentation skills and ability to effectively communicate and interact with internally and supplier's management highly required.
Strong ability to work in cross functional teams are required.
Job Type:Experienced Hire
Shift:Shift 1 (Japan)
Primary Location: Japan, Tokyo
Additional Locations:Japan, Nagoya
Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.