Director-FPGA RTL Design

Designation: Director-FPGA RTL Design
Bangalore
Job Description:
Ø As a director will be working on our existing and next generation Protocol Analysers and exercisers and similar products.
Ø Manages the FPGA design team
Ø Develop a new products to meet needs top semiconductor for their pre and post silicon validation
Ø The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab environment.
Ø The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in Verilog for targeted FPGA, writing test benches to validate the design etc.
Ø Job involves working with team of FPGA Design Engineers and deliver the products as planned
Ø Guides the team to Debugging of designs to resolve complex design issues.
Ø Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements.
Ø Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc.
Ø Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process.
Ø Maintaining all design documents and code base in Github
Ø Participate and Contribute to the standard bodies such as PCIeSig, MIPI Alliance, SD Association and USB Org
Ø Owns responsibility filing patents.
Ø International travel is involved
Qualifications:
BE/ME in Electronics from a reputed college. Specialization in VLSI and Embedded Design is a plus.
Ø 16 to 18 years of experience in designing and implementing FPGA based solution in Xilinx or Altera FPGA, preferably FPGA based product development experience.
Ø FPGA Based High speed IP development such as PCIe 5.0/6.0, USB4 or DP2.0
Ø Has expertise in verification of RTL code
Ø Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools.
Ø Deep expertise in FPGA based data plane design to manage the high-speed serial bus data
Ø Must have experience in Verilog and/or VHDL coding.
Ø Must have very good understanding of physical layer of SERDES of XILINX-AMD or Intel FPGA
Location: Bengaluru, India
Skills:
Xilinx
Altera
PCIe
USB
DP
Verilog
VHDL
Serdes
GiGE
UFS
CSI
DSI
MIPI
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"

Work arrangement
No