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Design-for-test architecture, insertion, and signoff for the full chip, including PHY and third-party IP DFT boundary conditions.
Scan chain insertion and compression (Tessent) across multi-clock digital logic.
ASA PHY DFT integration.
ASA IP DFT ports.
BIST PCS-PMA bus isolation.
Memory BIST (MBIST) for internal SRAMs/FIFOs; ATPG pattern generation and fault simulation.
IEEE 1149.1 JTAG controller integration; boundary scan for automotive test coverage.
Siemens Tessent or Synopsys DFT Compiler; prior automotive-grade DFT (AEC-Q100) experience preferred.
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