Memory Layout Engineer

Memory Layout Engineer (Senior / Lead / Manager)
Location: Bengaluru, Hyderabad
Experience Required: 3 to 15 Years
Employment Type: Full-Time
Job Summary:
We are seeking an experienced and detail-oriented Memory Layout Engineer with 3+ years of hands-on experience in custom layout design and verification of memory IPs (SRAM, ROM, CAM, etc.). The ideal candidate will have a strong background in advanced technology nodes and be well-versed in layout tools and methodologies.
Key Responsibilities:
Create and optimize transistor-level custom layouts for memory blocks (SRAM, ROM, eDRAM, CAM, etc.)
Work closely with circuit designers to ensure layout meets electrical and functional specifications.
Ensure designs meet DRC, LVS, ERC, and EM/IR requirements using industry-standard verification tools.
Perform parasitic extraction and assist in layout vs. schematic analysis and simulations.
Contribute to physical verification and sign-off processes.
Support tapeout activities and post-silicon validation as needed.
Collaborate with cross-functional teams across design, verification, and foundry interface.
About Company
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

Work arrangement
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