Senior Design Verification Engineer

Company Description Chiplogic Technologies (Chiplogic) is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML solutions. The organization delivers high-quality, dependable engineering services, including ODC and full turnkey semiconductor design from concept to silicon. Chiplogic also provides proof-of-concept development and complete IoT system solutions. In the AI/ML domain, the company builds services around its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, enabling advanced video and real-time dynamic applications. Team members collaborate in a technology-focused environment with opportunities to work on cutting-edge system and silicon designs.
Role Description We are seeking highly skilled SoC Design Verification Engineers with 4–8 years of experience in semiconductor verification, specifically in SoC-level verification. The ideal candidate should have hands-on experience in developing verification environments, creating test plans, debugging complex SoC issues, and driving verification closure for high-performance ASIC/SoC designs.
Key Responsibilities
Develop and execute comprehensive SoC verification plans based on design specifications.
Build and maintain reusable UVM/SystemVerilog-based verification environments.
Develop testcases, sequences, scoreboards, monitors, checkers, and coverage models.
Perform SoC-level verification involving multiple IPs, subsystems, processors, memories, and interconnects.
Execute regression suites, analyze failures, and drive bug resolution with design teams.
Work closely with RTL designers, architects, and firmware teams to ensure complete functional verification.
Perform coverage analysis and drive functional and code coverage closure.
Debug simulation failures and root-cause complex SoC integration issues.
Validate SoC functionality across power, reset, clocking, and performance scenarios.
Participate in verification reviews, test planning, and project milestone tracking.
Required Skills
4+ years experience in SoC Verification and ASIC verification methodologies.
Expertise in SystemVerilog and UVM.
Good understanding of SoC architecture, bus protocols, and subsystem integration.
Experience with industry-standard protocols such as:
AMBA AXI/AHB/APB
PCIe
USB
Ethernet
DDR/LPDDR (preferred)
Strong debugging skills using simulation and waveform analysis tools.
Experience with functional coverage, assertions (SVA), and coverage-driven verification.
Hands-on experience with EDA tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Knowledge of scripting languages such as Python, Perl, TCL, or Shell scripting.
Preferred Qualifications
Experience verifying complex SoCs involving CPUs, NoC, memory subsystems, and high-speed interfaces.
Exposure to low-power verification techniques (UPF/CPF).
Experience with Emulation/FPGA prototyping is an added advantage.
Understanding of Formal Verification methodologies is a plus.
Educational Qualification
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related fields.

Work arrangement
No