Design Verification Engineer

Digital verification methodology (UVM/OVM)
• SystemVerilog constrained-random verification
• Functional coverage & assertions (SVA)
• Interface protocols: PCIe, USB, DDR, Ethernet
• Simulation tools: Xcelium, VCS, Questa
• Debug: SimVision, Verdi
• Regression management & CI integration
• Strong scripting: Python, Perl, TCL"
Roles & Responsibilities:
• Lead functional verification of complex digital/mixed-signal IPs and subsystems.
• Develop and maintain UVM-based verification environments including scoreboards, monitors, and drivers.
• Write constrained-random test cases and functional coverage models.
• Define and track verification closure metrics and sign-off criteria.
• Collaborate with design and architecture teams to understand design intent and create verification plans.
• Perform root-cause analysis on simulation failures and regressions.
• Drive continuous improvement of verification methodology and infrastructure.
• Mentor junior verification engineers.
Required: Strong fundamentals in digital design and verification, hands-on UVM experience, proficiency in SystemVerilog and assertion-based verification."

Work arrangement
No