Senior Design Verification Engineer

Company Description Neurealm is an AI-first engineering partner that supports global enterprises in sectors such as healthcare, technology, semiconductors, commerce, industrial, and transportation. Its core platform, NeuGAIN, accelerates the enterprise AI journey across data, software development, process optimization, and IT operations. Neurealm’s capabilities span AI, Edge AI, Perception AI, digital platform engineering, data, cybersecurity, technology operations, silicon engineering, and embedded services. With teams across India, the US, Canada, Germany, and Japan, the company serves over 250 global enterprises. Guided by an engineering mindset and Neurealm Labs, it transforms ideas into practical solutions through modern offerings, frameworks, and strong technology and academic partnerships.
Role Description This full-time, on-site Senior Design Verification Engineer role is based in Bengaluru. The person in this role will define and execute verification plans for complex digital designs, including testbench architecture, test case development, and coverage analysis. They will collaborate closely with RTL designers and architects to understand specifications, review design implementations, and ensure functional correctness. Daily responsibilities include performing functional and formal verification, debugging failures, analyzing root causes, and driving resolution across cross-functional teams. The role also involves optimizing verification methodologies, mentoring junior engineers, and contributing to best practices that enhance silicon quality and time-to-market.
Qualifications
Strong foundation in Functional Verification and Formal Verification, with experience applying these methodologies to complex SoC or IP designs.
Proficiency in RTL Design and Computer Architecture, including understanding of microarchitecture, pipelines, memory subsystems, and bus protocols.
Advanced Debugging skills for simulation, emulation, and FPGA environments, including use of waveform viewers, log analysis, and issue tracking tools.
Hands-on experience with industry-standard verification tools and languages (e.g., SystemVerilog, UVM, simulators, formal tools).
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Proven background in silicon or ASIC/FPGA verification, with ownership of verification cycles from planning through tape-out or production release.
Ability to collaborate in cross-functional teams, communicate technical concepts clearly, and mentor less experienced engineers.
Experience with AI, Edge compute, or high-performance systems is an advantage, as is familiarity with scripting languages (e.g., Python, Perl, Shell) for automation.

Work arrangement
No