GLS Verification Engineer

Brief About Tech Mahindra – Silicon Engineering
Tech Mahindra Silicon Engineering is a key part of Tech Mahindra’s semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, networking, and industrial clients. The practice focuses on VLSI, Embedded Systems, SoC Design, and Platform Engineering, supporting customers from architecture and RTL design through implementation, verification, validation, and post-silicon support.
The Silicon Engineering unit works across IP, Sub-System, and SoC-level development, offering deep expertise in areas such as Physical Design, RTL Design, Design Verification, DFT, Analog/Mixed-Signal Design, Post-Silicon Validation, Embedded Software, and System Engineering. Teams leverage industry-leading EDA tools and advanced implementation methodologies to deliver high-performance, low-power, and manufacturable silicon solutions.
Backed by Tech Mahindra’s global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology companies worldwide, serving as an extended engineering arm to accelerate silicon development programs, optimize design quality, and enable faster time-to-market for next-generation SoCs and products.
About the Role – GLS Verification Engineer
In this exciting role, you will be responsible for Gate-Level Simulation (GLS) Verification of complex IPs, subsystems, and SoCs to ensure functional correctness, timing accuracy, reset behavior, low-power intent validation, and silicon readiness before tape-out. You will work closely with RTL Design, Design Verification, DFT, STA, Physical Design, and Low-Power teams to identify and resolve issues that may not be visible in RTL simulations.
The role involves setup and execution of gate-level simulations, SDF annotation, timing violation analysis, X-propagation debugging, reset validation, power-aware GLS, and signoff verification activities using industry-standard EDA tools and methodologies.
Responsibilities – Key Responsibilities
Execute Gate-Level Simulations (GLS) for IP, subsystem, and SoC-level designs using netlists generated from synthesis and implementation flows.
Perform SDF annotation and timing-aware simulations to validate setup, hold, recovery, and removal timing requirements.
Analyze and debug timing violations, race conditions, metastability issues, and X-propagation behaviors.
Validate reset sequences, clock-domain crossings (CDC), reset-domain crossings (RDC), and power-up initialization scenarios.
Support Low-Power GLS Verification involving UPF/CPF, power gating, retention, isolation, and state restoration checks.
Collaborate with RTL, Physical Design, STA, DFT, and Design Verification teams to identify and resolve implementation-related issues.
Perform post-synthesis and post-layout functional verification to ensure design equivalence and correctness.
Analyze simulation logs, waveform dumps, and timing reports to root-cause GLS failures.
Develop and enhance automation frameworks for GLS execution, regression management, and report generation.
Create verification plans, coverage reports, debug documentation, and signoff reports.
Participate in design reviews, customer discussions, and methodology improvements to enhance GLS quality and efficiency.
Support tape-out readiness activities by ensuring all critical GLS signoff criteria are successfully closed.
Collaborate with global engineering teams to meet project milestones, quality targets, and silicon schedules.
Qualifications
BE/BTech/ME/MTech degree in Electronics, Electrical, Telecommunications, Microelectronics, VLSI Design, Computer Engineering, or related engineering disciplines.
Required Skills
Strong experience in Gate-Level Simulation (GLS) Verification for ASIC/SoC designs.
Hands-on expertise in post-synthesis and post-layout netlist verification methodologies.
Solid understanding of SDF annotation, timing checks, setup/hold analysis, recovery/removal checks, and timing closure concepts.
Strong knowledge of Verilog/SystemVerilog and simulation concepts.
Hands-on experience with simulators such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim/ModelSim, or equivalent.
Experience working with Low-Power Verification methodologies using UPF/CPF.
Knowledge of CDC, RDC, DFT, ATPG, Scan, and MBIST validation flows.
Understanding of ASIC implementation flow including Synthesis, Physical Design, STA, and Signoff Verification.
Exposure to advanced technology nodes such as 7nm, 5nm, 3nm, or below is preferred.
Strong debugging, analytical, problem-solving, communication, and stakeholder management skills.
Ability to work effectively with cross-functional global engineering teams in fast-paced semiconductor development programs.
Preferred Experience
4 to 10 years of experience in GLS Verification, Design Verification or SoC Verification.
Experience with complex CPU, GPU, AI/ML, Networking, Automotive, Storage, or Multimedia SoCs.
Exposure to power-aware simulations, timing signoff checks, and silicon correlation methodologies.
Familiarity with modern verification environments involving UVM, assertions, functional coverage, and emulation/prototyping platforms.
Location
Bangalore

Work arrangement
No