Senior Static Timing Analysis (STA) Engineer

Senior STA Engineer – 3 to 5 Years
Handle block-level STA and basic timing closure
Identify missing constraints, unconstrained paths, and clock definition issues
Assist in setup and hold violation debug
Generate timing reports and support signoff activities
Lead STA Engineer – 6 to 9 Years
Own block and subsystem-level STA from early analysis to signoff
Develop complete SDC constraints including false and multicycle paths
Perform cross-domain and interface timing analysis
Drive timing ECO strategies such as buffering and VT swaps
Support low-power and multi-voltage timing scenarios
Tools & Skills
Static Timing Analysis: Synopsys PrimeTime (DMSA), Cadence Tempus
Timing Concepts: OCV, AOCV, POCV, CRPR, Signal Integrity
Physical Design Awareness: ICC2, Fusion Compiler, Innovus
Low Power Timing: UPF/CPF, power-gated designs
Scripting: Tcl (mandatory), Perl/Python (preferred)

Work arrangement
No