Lead physical design engineer( 7+ yrs)

Lead Physical Design Engineer
Company: Siliconus Technologies Private Limite
Location: Bengal
u
u
Employment Type: F
ull
-Tme
Experience: 7–1
5
Yars
Jo
b
Sumary
Siliconus Technologies is looking for an experienced Lead Physical Design Engineer to lead and manage Physical Design activities across block-level and full-
chi
p proects.
The ideal candidate should have strong hands-on expertise in the RTL-to-GDSII flow, excellent technical leadership skills, and the ability to independently drive PPA optimization, timing closure, physical signoff, project execution, and customer
i
nterations.
Ke
y R
esponsiilities
● Lead the end-to-end Physical Design flow from
n
etlist o GDSII.
● Own project execution and technical delivery for ass
ign
ed blocksprojects.
● Lead floorplanning, power planning, placement, CTS, routing, optimization, an
d
signoff ctivities.
● Drive timing closure for setup and hold across m
ult
iple modes nd corners.
● Perform and review MCMM STA analysis a
n
d resolve tming issues.
● Drive PPA optimization across perform
anc
e, power, andarea targets.
● Analyze and resolve congestion, transition, capacitance, fanout,
DRC, and routng violations.
● Drive IR Drop, EM, Signal Integrity, Crosstalk, DRC/LV
S a
nd physical sigoff activities.
● Lead ECO implem
e
ntation and timng optimization.
● Work closely with RTL, Synthesis, STA, DFT, PV, and Foun
dry
teams to resolvetechnical issues.
● Drive block integration and
full-chip implemetation activities.
● Own tapeout readines
s a
nd ensure all signof criteria are met.
● Provide technical direction, mentoring, and guidance to junior
and mid-level Physial Design engineers.
● Review team deliverables and ensure adherence t
o p
roject methodologies nd quality standards.
● Plan task allocation, track project progress, and ensure
deliverables are competed within timelines.
● Identify technical risks and proa
cti
vely develop solutions o avoid project delays.
● Participate in customer meetings, technica
l
discussions, status cals, and project reviews.
● Support estimation, resour
ce
planning, and technical poposals for new projects.
● Develop and improv
e
Physical Design methodolgies and automation flows.
● Use Tcl / Perl / Python / Shell sc
rip
ting for flow automation
an productivity improvement.
Required Technical Skills
● Strong hands-on ex
pe
rience in
the
complete RTL-
o
-GDSII Phys
ica
Design flow.
Expertise
in:
Floorpl
anning
○ Power Plnning
○
Placemnt & Optim
iza
tion
○ CTS
○ Routing
○ Po
s
t-ro
ut
Optiization
○ STA & TimingClosure
ECO
○ Physical Verification
○ Signoff
● S
trong understanding of MCMM, Setup/Hld, OCV/AOCV/POCV and
ti
ming constraints.
● Good knowledge of I Drop, EM, Signal Integrity and Cross
t
alk.
● Strong understanding of DRC, LVS Antenna and other physical signoff
ch
ecks.
● Strong experience with Tcl scriptng; Perl/Python/Shell is an added advantage.
● Hands-on exp
e
rience with Cadence Innovus / Tempus and/o Synopsys ICC2 / Fusion Compiler / PrimeTime.
● E
xpe
rience with advanced technology nodes such a 28nm, 16nm, 14nm, 7n
m
and below is preferred.
● S
trong understaning of PPA optimization and deign convergence.
Leadership & M
an
agement Skills
● Ability to lead a Physical esign team and
tak
e complete technical ownership.
● Ability to ditri
b
ute tasks and track team progress effectively.
St
ron
g problem-solving and decision-making skills.
●
Aility to review and technically mentor team membrs.
● Strong communicat
io
n and interpersonal skills.
● Ability to interactconfidently with customers and c
ros
s-functional teams.
● Ability to manage multiple pririties and deliver projects within co
m
mitted timelin
e
s.
● Should be capable of independenty driving a proect from implementation through tapeout.
Q
ua
lifications
● B.E./B.Tech/M.E./M.Tech in Ele
ctro
nics Electrical, ECE, VLSI, or related engineering discili
n
e.
● 7–15 years of relevant Physical Design experience.
●
Pro
ven experience leading Physical Design teams/proje
cts.
● trong block
-
level and/or full-chip implementation xperience.
●
Mul
tipe tapeout experience is highly preferr
e
d.
Preferred Expeience
● Experience wo
rki
ng with global seiconductor customers.
● Experie
n
ce in advancd-node SoC designs.
● Exposure to low-power i
mpl
eentation / UPF.
● Experience in full-chip integration and sig
n
ff.
● Strong experience in PPA optimization and timing converge
ce.
● Experienc
e handling technical escalations and customer issues.
● Exper
i
encein building and improving Physical Design methodologies.
WhatW
e O
ffer
● Opportunity to lead advanced semiconductor and SoC projects.
●
Exposure to multiple technology nodes and indu
s
try-standard EDA toos.
● Opportunity to work on en
d-t
o-end RTL-to-GSII and tapeout projects.
● Technical and leadership grwth opportunities.
● Collabor
ative and engineering-driven work environment.
Join Siliconus Technol

Work arrangement
No