Lead – SerDes Design Engineer

Lead – SerDes Design Engineer
Location: Bangalore
About Phytau Semiconductors
Phytau Semiconductors is a specialist semiconductor design company built around one core strength: solving difficult analog and high-speed silicon problems.
We specialize in Analog, Clocking, and SerDes, with deep expertise in the circuits that determine the performance of modern high-speed chips. Our work spans high-speed SerDes, PLLs, CDRs, injection-locked oscillators, clocking architectures, and precision analog—from architectural decisions down to transistor-level implementation.
We believe the hardest semiconductor problems are rarely solved by circuit design alone. They require a combination of strong fundamentals, architectural insight, attention to implementation, and relentless silicon-oriented debugging. This is the engineering culture we have built at Phytau.
Our engineers take end-to-end ownership—from understanding the system problem and defining the architecture, through circuit design, simulation, layout interaction, post-layout optimization, and silicon bring-up.
We partner with semiconductor companies that need deep analog expertise without compromising on execution. Whether it is pushing the limits of speed, jitter, power, or performance, Phytau brings the technical depth and ownership needed to turn challenging specifications into working silicon.
We don't aim to be the largest design team. We aim to be the team you call when the silicon problem is hard.
Lead – SerDes Design Engineer
Experience: 5–8 Years
Location: India
Employment Type: Full-time
About the Role
We are looking for a hands-on Lead SerDes Design Engineer to lead the design and development of high-speed SerDes circuits and systems. The role involves architecture, circuit design, system-level analysis, technical leadership, and silicon bring-up.
Key Responsibilities
Lead high-speed SerDes design from architecture and specification through silicon.
Design and optimize analog/mixed-signal blocks for high-speed data links.
Perform transistor-level design, simulation, PVT analysis, Monte Carlo, and post-layout verification.
Analyze jitter, noise, bandwidth, eye opening, BER, power, and signal integrity.
Drive layout reviews and parasitic-aware design optimization.
Support silicon bring-up, characterization, and debug.
Mentor junior engineers and lead technical design reviews.
Preferred SerDes Design Experience
Experience in one or more of the following:
High-speed TX/RX architectures
CDRs and PLLs
TX drivers and output stages
CTLE / VGA / equalization circuits
Decision Feedback Equalizers (DFE)
Comparators and samplers
Phase interpolators and clock/data recovery
SerDes clocking and high-speed clock distribution
PAM4 / NRZ signaling
High-speed I/O and electrical interfaces
Required Technical Skills
Strong fundamentals in analog and mixed-signal IC design.
Strong understanding of high-speed circuit design, feedback, noise, jitter, bandwidth, and signal integrity.
Hands-on experience with Cadence Virtuoso/Spectre or equivalent tools.
Experience with PVT, Monte Carlo, transient, AC/noise, and post-layout simulations.
Good understanding of high-speed analog layout and parasitic effects.
Leadership Responsibilities
Own assigned SerDes blocks and drive execution from architecture to silicon.
Provide technical guidance and mentorship to junior engineers.
Conduct circuit and design reviews.
Identify technical risks and drive their resolution.
Collaborate with system, layout, verification, digital, and application teams.
Education
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or a related field.
Experience
5–8 years of industry experience in Analog/Mixed-Signal IC Design, preferably with hands-on experience in high-speed SerDes design.
What We Are Looking For
Strong hands-on SerDes/analog designer with an ownership mindset.
Ability to independently take designs from architecture to silicon.
Strong circuit-level analysis, debugging, and problem-solving skills.
Ability to mentor engineers while remaining actively involved in design.
Good communication and cross-functional collaboration skills.
Good to Have
Experience with advanced CMOS/FinFET technologies.
Experience with 25G/56G/112G+ SerDes.
Experience with PAM4, NRZ, PCIe, Ethernet, or other high-speed interfaces.
Silicon bring-up and characterization experience.
Experience with high-speed measurement, eye diagrams, BER, jitter, and compliance testing.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"

Work arrangement
No