Lead Engineer

Job Requirements
At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.
Role Overview
Own day-to-day physical implementation of an assigned tile/block from netlist and constraints through routed, timing-clean and signoff-ready handoff. Candidates must demonstrate real implementation ownership rather than only flow execution or monitoring.
Key Responsibilities
Validate netlist, libraries, constraints and floorplan inputs; identify readiness gaps
Execute floorplanning, power planning, placement, CTS, routing and post-route optimisation
Analyse congestion, utilisation, clock skew/latency, timing paths and route quality
Fix setup/hold, transition, capacitance, fanout, noise and design-rule violations
Generate and implement timing/physical ECOs and verify closure across required modes and corners
Support extraction, STA, LEC, physical verification and IR/EM readiness checks
Maintain run summaries, QoR comparisons, issue logs and closure status
Work closely with tile lead, STA, RTL, DFT and integration teams to resolve dependencies
Required Skills & Expertise
3-8 years of relevant ASIC physical design experience with hands-on tile/block PnR work
Experience with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler
Practical knowledge of floorplanning, placement, CTS, routing and optimisation
Ability to read timing reports and perform setup/hold debugging using PrimeTime and/or Tempus
Familiarity with parasitic extraction using StarRC or equivalent
Working knowledge of LEC and physical verification concepts
Strong problem-solving, ownership and communication skills
Experience Calibration
3-5 years: Must independently execute major PnR stages, analyse reports and close common timing/physical violations with review support
6-8 years: Must independently own full tile closure, drive ECO convergence, review QoR, manage dependencies and guide junior engineers
Preferred Skills
Exposure to RedHawk/Voltus and Calibre/Pegasus-class signoff checks
TCL scripting capability; Python is an advantage
Experience on advanced-node designs without sharing proprietary design information
Recruiter Knockout Questions
Which tile/block did the candidate personally own, and from which stage to which final handoff?
Which PnR tool and implementation stages were used hands-on in the most recent project?
Can the candidate describe one setup/hold, congestion or CTS issue they diagnosed and closed?
Has the candidate implemented ECOs and verified closure across multiple modes and corners?
Was the role true block ownership, or limited to running flows and reporting results?
Education
BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline
We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.
We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Work arrangement
No