ASIC Digital Design, Staff Engineer

ASIC Digital Design, Staff
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation.
You Are:
You are a Staff ASIC Digital Design Engineer who owns a PCIe subsystem end to end. You turn architecture into solid micro-architecture and production RTL, and you are the technical owner for that area across configurations, reviews, and debug.
You have substantial experience designing complex high-speed interface IP in RTL. You know PCIe well—or you have done equivalent work on CXL, AMBA, DDR, UCIe, or similar protocols. You work across clocking, resets, flow control and low power, and making parameterized RTL maintainable.
You can mentor senior and junior designers through reviews and guidance, and you drive issues to closure with verification, formal, and physical design.
What You'll Be Doing:
Own RTL and micro-architecture for one or more PCIe controller subsystems or major features (block through subsystem integration).
Write design specs, implement production RTL, and drive your area through verification, synthesis/timing closure support, and design convergence.
Resolve complex design and debug issues in your domain; escalate architecture trade-offs with clear options.
Participate in and lead design reviews; enforce coding standards, CDC/RDC, and quality for your code.
Collaborate with verification, formal, emulation, and physical design to close bugs and integration issues.
Support post-silicon and customer debug for your area.
Mentor Senior and junior engineers; grow toward broader architectural influence.
Communicate status, risks, and dependencies for your subsystem.
The Impact You Will Have:
Deliver robust, high-quality PCIe subsystem RTL that scales across products and configurations.
Drive code quality and features in your area.
Accelerate team execution by being a reliable technical owner and mentor.
Contribute to silicon-proven PCIe IP for commercial, enterprise, and automotive customers.
What You'll Need:
BSEE with 8+ years of relevant experience, or MSEE with 6+ years.
Proven ownership of complex ASIC RTL (subsystem or large block), from spec through tapeout or IP release.
Strong experience in PCIe digital design, or a similar high-speed protocol (CXL, AMBA interconnect, DDR controller, UCIe, Ethernet MAC, or equivalent)
Proven on ASIC fundamentals: synthesizable RTL, clocking, CDC/RDC, resets, low power, and DFT awareness.
Ability to define micro-architecture for the area you own and work from architecture specs.
Experience with parameterized / configurable IP is a strong plus.
Scripting (Python, TCL, Perl) desirable. AI-assisted design tools a plus.
Who You Are:
A subsystem owner
Hands-on in RTL and precise in reviews.
Collaborative with DV and PD; you close the loop and make the difference.
A mentor to other designer, with ability to ensure code quality.

Work arrangement
No