Principal Physical Design Floorplan Engineer

www.EnchargeAi.com
Location : Bangalore
Principal Physical Design Floorplan Engineer
Bangalore
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Experience: 14-20 Years
Location: Bangalore/2 days to work
Department: RTL-to-GDSII / Physical Implementation
Role Overview
We are seeking a high-caliber Principal Physical Design Engineer with a specialized mastery of Floorplanning design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum.
As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.
Key Responsibilities
Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs.
Cross-Functional PPA Trade-offs: Collaborate directly with RTL and Architecture teams. You will use "Design Thinking" to influence the micro-architecture, suggesting changes to bus widths, pipeline stages, or memory configurations to optimize physical outcomes.
Methodology Development: Establish best practices and automated flows for floorplanning to be used by the wider implementation team.
Technical Requirements
Core Experience: 14-20+ years in Physical Design with a proven track record of multiple successful tape-outs at advanced nodes (7nm, 5nm, or 3nm).
Floorplanning Savvy: Deep proficiency in hierarchical physical design and top-level integration using industry-standard tools (Innovus or IC Compiler II).
Scripting: Advanced proficiency in Tcl, Python, or Perl to automate complex floorplanning tasks and data analysis.
Behavioral Attributes
Critical Thinker: You don't just follow a recipe. You question constraints and look for "hidden" PPA gains.
Design Thinking: Ability to empathize with the challenges of upstream (RTL) and downstream (Sign-off) teams to create a holistic solution.
Influence: You can articulate technical trade-offs to stakeholders,
Education
B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent.
Skills
Innovus
ICC2
2nm
3nm
TCL
Python
Perl
"Hierarchial Physical design"
'Large-scale SoC Design"
Contact:
Uday
muday_bhaskar@yahoo.com
Mulya Technologies

Work arrangement
No