Full Chip STA with 2 to 4 yrs of Experience

Role Descr</strong>iption The Full Chip STA Engineer will be responsible for performing end-to-end static timing analysis for complex ASIC and SoC designs, ensuring robust timing closure across multiple corners, modes, and technology nodes. Day-to-day responsibilities include building and maintaining STA constraints, running full-chip timing signoff flows, debugging violations, collaborating closely with RTL, physical design, and DFT teams, and driving timing ECOs to achieve signoff-quality results. The role involves analyzing signal integrity, clock trees, on-chip variation, and low-power features, while aligning timing requirements with performance, power, and area goals. The engineer will prepare clear documentation, reports, and signoff summaries, participate in design reviews, and support tape-out schedules for global customers. This is a full-time, on-site role based in Bengaluru.
Qualifications
Candidates should possess strong skills in static timing analysis, full-chip timing closure, and signoff methodologies across advanced and mature technology nodes.
Candidates should possess expertise in STA tools and flows (e.g., PrimeTime or equivalent), including constraint development (SDC), timing ECO implementation, and analysis of multi-corner, multi-mode scenarios.
Candidates should possess solid understanding of physical design concepts such as clock tree synthesis, placement and routing, signal integrity, on-chip variation, and low-power implementation techniques.
Candidates should possess knowledge of digital design fundamentals, RTL design, synchronous design principles, and familiarity with DFT and functional verification impacts on timing.
Candidates should possess strong problem-solving skills, attention to detail, and the ability to collaborate effectively with cross-functional engineering teams in fast-paced project environments.
Beneficial qualifications include experience with advanced nodes (e.g., 7nm and

Work arrangement
No