Live opening · Posted 8 days ago

Sr. Principal Product Engineer

Cadence Design Systems · HOME CA
Workday
You are 8 days behind. JobBeeper subscribers saw this role while it was still new.

At a glance

The key details from the original listing.

Posted 8 days ago
CompanyCadence Design Systems
LocationHOME CA
SourceWorkday
Listed8 days ago

Your early-applicant advantage

Live timing from JobBeeper.

Live data
0 min from Workday publishing this role to us finding it
10 min median time from a role going live to a subscriber being told
6 hours subscribers had this role before this page existed
72,286 roles found in the last 24 hours — the newest are not on this site yet
Start your free trial →

About the role

Description supplied by the original job listing.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.
You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.
You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.
You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.
You are an excellent communicator.
Position Responsibilities:
Support Cadence products in the Digital and Signoff team.
Track and debug customer issues and work with R&D and release team on issue resolution.
Run design benchmarks and develop flows and solutions.
Position Requirements:
MS in EE with 2+ years of experience in Digital Implementation, either as a design engineer or as a product engineer
Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.
Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.
Exposure to, and solid understanding of, hierarchical design methodologies and low power design
Energetic team player with a passion for problem solving
Strong analysis skills with a track record to prove it
Strong communication skills (verbal and written)
Automation skills using Perl, Tcl and shell scripting
The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.

Get JobBeeper Mobile App

Never miss a job opening! Get instant job alerts on your phone.

Subscribers see fresh openings within minutes. Download the JobBeeper App on Google Play to get real-time push notifications and apply before anyone else.

⚡ Instant Push Alerts 🎯 Tailored Filters 🚀 Direct Employer Links
GET IT ON Google Play

More openings worth a look

Recently tracked roles with full details and direct application links.

6 roles
Good roles move before most people even see them. Tell JobBeeper what you want and get fresh matches delivered in minutes.
Start your free trial →
⚡ Get fresh job alerts 📱 Get App