Design Verification - SOC, IP, Subsystem

We are hiring Design Verification Engineers [DV]:
Experience Required: 4 to 10+ years (Without training or internship)
Location: Bengaluru
Education : BE/BTech/ME/MTech
“Your reference would be greatly appreciated”
Job Summary:
We are seeking a passionate and experienced Design Verification Engineer. The ideal candidate will have strong hands-on experience with UVM methodology, and a solid understanding of SoC/IP-level verification flows. Good to have GLS, UPF, Low power experience, ARM, Pcie, Ethernet, USB,MIPI.
Required Skills & Qualifications:
• Experience in ASIC/IP/SoC verification.
• Must have good knowledge on the verification flows
• Experience developing testbenches for block level or IP level or SOC Level verification.
• Experience of working in complex test-bench/model in Verilog, System Verilog or System C
• Developing and maintaining block level test benches
• Proficient in SystemVerilog, UVM, and testbench architecture.
• Proficient in Memory, DDR, DRAM, Verification
• Strong knowledge of AMBA protocols (AXI, AHB, APB).
• Hands-on experience with simulation tools (VCS, Questa, XSIM, etc.).
• Familiarity with debug tools (Verdi, DVE) and waveform analysis.
• Solid understanding of functional coverage, assertions, and scoreboarding.
• Experience in writing automation scripts using Python/Perl/TCL
Share your updated CV / resume to vagdevi@semi-leaf.com

Work arrangement
Hybrid