Live opening · Posted 7 days ago

Senior Physical Design Engineer

Interex semiconductor · Bengaluru, Karnataka, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 7 days ago
CompanyInterex semiconductor
LocationBengaluru, Karnataka, India (On-site)
Work modeNo
SourceLinkedin
Listed7 days ago

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About the role

Description supplied by the original job listing.

Company Description Interex Semiconductor delivers custom ASICs, silicon IPs, and end-to-end semiconductor solutions and services to global clients. The company focuses on innovation and high-quality engineering to help customers differentiate in a fast-changing technology landscape. Interex Semiconductor is committed to long-term partnerships, offering expertise that spans design, verification, and implementation. As the organization continues to shape the semiconductor industry, it emphasizes a collaborative environment where technical excellence and customer success drive growth.
Role Description The Senior Physical Design Engineer will lead and execute block-level and chip-level physical design activities, including floorplanning, partitioning, placement, clock tree synthesis, routing, and timing closure for complex ASICs. The role involves collaborating closely with RTL design, logic design, and verification teams to ensure robust implementation, performance, and power optimization. Daily responsibilities include running and analyzing physical verification, resolving design rule and layout-related issues, and driving sign-off for timing, power, and signal integrity. The engineer will also contribute to methodology improvements, tool flows, and best practices, mentoring junior team members and supporting project planning and reviews. This is a full-time, on-site role based in Bengaluru.
Qualifications
Candidates should possess strong skills in Physical Design, including floorplanning, placement, CTS, routing, and timing closure.
Candidates should possess skills in Logic Design and Circuit Design to understand functionality, timing, power trade-offs, and design constraints.
Candidates should possess skills in RTL Design, with the ability to interpret RTL, constraints (SDC), and interface specifications for implementation.
Experience with industry-standard EDA tools (e.g., Cadence, Synopsys, or equivalent) and advanced technology nodes is highly beneficial.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field, with several years of relevant ASIC implementation experience.
Strong analytical, problem-solving, and communication skills, with the ability to work collaboratively in cross-functional engineering teams.

Work arrangement
No

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