SoC Architect (VLSI)

Role: SoC Architect – RISC-V / AI Accelerator (VLSI)
Experience: 5–7 years
Location: Trivandrum, Kerala
Work Mode: Hybrid
We are looking for a hands-on SoC Architect. You will shape the architecture, make and defend the key trade-offs, write and review RTL, and bring the design up on FPGA. You will also help build the design, verification and tapeout practice around it. If you want to see a chip through from blank page to silicon, and have real influence over how it's built, this role is for you.
Must-Have Qualifications
B.Tech/M.Tech in Electronics, Electrical, VLSI or Computer Engineering.
5–7 years in SoC or ASIC design, with at least 2–3 years in architecture, micro-architecture or subsystem ownership.
Strong hands-on SystemVerilog RTL design and integration of multi-IP subsystems.
Solid understanding of processor-based SoCs: CPU subsystems, caches, coherency basics, AMBA AXI/AHB/APB, DMA, interrupt controllers and memory controllers.
Working knowledge of RISC-V (ISA, privilege spec, platform-level components such as CLINT/PLIC) or equivalent ARM Cortex-A/M experience with willingness to move to RISC-V.
Experience with FPGA prototyping of complex designs (Vivado, timing closure, debug with ILA or similar).
Exposure to the full front-end flow: specification, RTL, lint/CDC, synthesis and verification sign-off, plus a working understanding of the back-end flow.
Ability to model and reason about performance and power trade-offs early, with partial data.
Clear written specifications and confident technical communication.
Good-to-Have
Experience with open-source RISC-V cores (CVA6, CV32E40P, Ibex, BOOM, etc.) or SoC frameworks (ESP, OpenPiton, PULP).
Experience with ML accelerators or NPUs such as NVDLA, systolic arrays or dataflow engines, or with quantization, tiling and memory-bandwidth analysis for CNN/transformer workloads.
Having taken a chip to tapeout, including shuttle or MPW programmes.
Low-power design (UPF, power gating, DVFS) and DFT (scan, MBIST, JTAG).
Linux bring-up on custom hardware, device trees, OpenSBI/U-Boot.
Familiarity with functional safety (ISO 26262) or security (secure boot, root of trust) for automotive and industrial silicon.
Scripting in Python/Tcl, and experience with verification frameworks such as UVM or cocotb.

Work arrangement
Hybrid