Physical Design Engineer

Company Description EdgeSilica Private Limited is a semiconductor services company specializing in VLSI design and engineering solutions for global customers. The organization focuses on physical design, design verification, SoC development, and system software to help clients reduce time-to-market while maintaining strong engineering quality. EdgeSilica supports startups, fabless companies, and product organizations with process-driven execution and a customer-first approach. Teams work with industry-standard EDA tools and follow best practices in design quality, scalability, and confidentiality. The company is committed to delivering reliable, scalable, and future-ready semiconductor engineering services through long-term partnerships and flexible engagement models.
Role Description This is a full-time, on-site Physical Design Engineer role based in Hyderabad. The Physical Design Engineer will be responsible for implementing RTL to GDSII flows, including floorplanning, placement, clock tree synthesis, routing, and sign-off activities. Day-to-day work includes timing closure, power and area optimization, physical verification (DRC/LVS), and collaborating with RTL, verification, and architecture teams to resolve design issues. The role also involves using industry-standard EDA tools, creating and maintaining scripts for automation, reviewing constraint files, and ensuring design quality, scalability, and manufacturability. The engineer will contribute to project planning, documentation, and continuous improvement of design methodologies.
Qualifications
Strong foundation in VLSI fundamentals, digital design concepts, and CMOS technology.
Hands-on experience with physical design flows (floorplanning, placement, CTS, routing, optimization, and sign-off).
Proficiency with industry-standard EDA tools for physical design and STA (e.g., Cadence, Synopsys, or Siemens tools).
Skills in timing analysis and closure, including working with constraints, clock domains, and multi-mode multi-corner scenarios.
Knowledge of power, performance, and area optimization techniques, as well as IR drop and electromigration analysis.
Experience with physical verification (DRC/LVS), layout quality checks, and resolving design-rule violations.
Ability to write and maintain automation scripts (e.g., Tcl, Python, or Shell) to improve design productivity and consistency.
Effective collaboration skills for working with RTL, verification, and architecture teams, and clear written and verbal communication.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related discipline.
Prior experience in ASIC/SoC physical design projects is preferred; exposure to advanced technology nodes is an advantage.

Work arrangement
No