RTL Design Engineer

Company Description PravegaSemi Pvt. Ltd. is an engineering and R&D services partner focused on helping global semiconductor companies develop next‑generation chips. The company specializes in end‑to‑end chip development across digital frontend (ASIC design and verification, post‑silicon validation, FPGA validation and emulation), digital backend (physical design, synthesis, RTL to GDSII, static timing analysis, analog and mixed-signal), and embedded systems prototyping and validation. Founded by young and energetic frontend engineers, PravegaSemi emphasizes expert consultation and leadership that co‑executes projects, not just provides resources. Team members are encouraged to be inquisitive and stay current with semiconductor trends through a strong, mature training platform. This environment offers growth opportunities for engineers passionate about cutting‑edge semiconductor technologies.
Role Description The RTL Design Engineer will work on full‑cycle digital design tasks, translating specifications into synthesizable RTL for complex ASIC and FPGA solutions. Responsibilities include micro‑architecture definition, RTL coding in HDLs (such as Verilog/SystemVerilog), integration of IP blocks, and collaboration with verification teams to ensure design quality and coverage. The role involves timing‑aware coding, lint and CDC checks, support for synthesis and physical design teams, and participation in design reviews and documentation. The engineer will also help debug issues in simulation and, when required, support post‑silicon and FPGA validation teams. This is a full‑time, on‑site role based in Bengaluru South, working closely with cross‑functional semiconductor design and verification teams.
Qualifications
Strong proficiency in Design Engineering for digital hardware, including RTL development, micro‑architecture, and IP integration.
Solid understanding of Electrical Engineering fundamentals relevant to semiconductor design, such as digital logic, timing, and signal integrity.
Experience with Computer‑Aided Design (CAD) and EDA tools used for RTL design, synthesis, linting, and static timing analysis.
Exposure to Product Design concepts in semiconductor or embedded systems, focusing on reliability, scalability, and manufacturability.
Hands‑on experience with Verilog/SystemVerilog or VHDL and familiarity with industry‑standard flows for ASIC/FPGA development.
Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or a closely related field.
Ability to collaborate in cross‑functional teams, communicate design intent clearly, and document specifications and design decisions.
Interest in continuous learning, staying updated with semiconductor design methodologies, and participating in internal training programs.

Work arrangement
No