Lead Verification Engineer - PCIE/CXL

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
MTS SILICON DESIGN ENGINEER
The Role
As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.
The Person
You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsiblities
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
Build the directed and random verification tests
Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality
Preferred Experience
8-10 Years of Experience in ASIC Verification
Experience with PCIe or CXL or ethernet protocols is a must
Proficient in IP level ASIC verification
Expert in Verilog, System Verilog, Object Oriented programming
Expertise in developing UVM based verification frameworks and testbenches
Scripting and automation of verification processes and flows
Exposure to leadership or mentorship is an asset
Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Comfortable in python / Perl and editing / maintaining scripts
Strong communication skills and the ability to work independently as well as in a cross-site team environment
Good Computer Architecture, systems knowledge is a plus
Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus
Academic Credentials
Bachelors or Masters degree in computer engineering/Electrical Engineering
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Work arrangement
No