[EMN] Senior IP Design Verification Engineer (5-10 YoE) (with Joining Bonus)

🎁Q4 JOINING BONUS
Join BGSV by 31 December 2026 and receive a Joining Bonus equivalent to 1 month gross salary, subject to program eligibility and terms & conditions.
About the Role
As a Senior IP Design Verification Engineer, you will play a key role in ensuring the functional correctness, interoperability, and quality of advanced Silicon IPs for next-generation System-on-Chip (SoC) platforms. You will own pre-silicon verification from planning through sign-off, developing robust UVM/SystemVerilog verification environments and driving complex debugging across IP and system boundaries. You will work with advanced interfaces and protocols, including UCIe and AXI, while contributing to the technical excellence of Bosch’s Automotive Chiplet Systems (ACS) project.
Learn more about Bosch’s Automotive Chiplet technology: https://www.bosch-semiconductors.com/stories-and-events/chiplet-revolution/
Responsibilities
Own and execute Silicon IP based pre-silicon verifications (verify e.g. UCIe Interoperability) from planning through verification sign-off.
Develop, enhance, and maintain verification environments, testbenches, test cases, checkers, and coverage models.
Run simulations and regressions, analyze failures, debug issues, and drive root-cause resolution with IP, integration, and system teams.
Track verification progress, report status clearly, highlight risks early, and propose mitigation actions.
Review verification results, ensure process compliance, and contribute to technical reviews and design-verification discussions.
Guide junior engineers on verification methodology, debugging approach, and efficient execution of assigned tasks.
Technical expertise
Have 5-10 years of experience working as a Design Verification
Solid knowledge of the ASIC/SoC development lifecycle.
Hands-on experience with OVM/UVM methodologies using System Verilog.
Experience in testbench development or enhancement, test case creation, coding, execution, bug investigation, regression runs, coverage analysis, and verification sign-off.
Experience with AXI VIP and AXI protocol verification.
Hands-on experience with UCIe is highly preferred.
Familiarity with widely used standards and protocols such as PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C,...
Experience performing gate-level simulations and timing constraint simulations
Strong root cause analysis and debugging skills with the ability to isolate issues across testbench, integration, and IP boundaries.
Fluent in written and spoken English
Personality and Working Practice:
You thrive in a dynamic and fast-paced work environment, embracing challenges and change.
You work proactively, self-organized and you are keenly interested in taking over responsibility.
You are highly collaborative and eager to contribute to team success, with a strong willingness to continuously learn and improve.
Your "out-of-the-box thinking" helps to achieve creative and effective solutions to complex problems.
You exhibit a hands-on mentality, eager to delve into technical details and provide direct support to developers and team members.
You are highly motivated in tailoring and optimizing processes to enhance efficiency and overall project outcomes.
Education
Bachelor’s degree in Electronics, Electrical Engineering, or a comparable discipline.

Employment type
Full-time

Work arrangement
No