Live opening · Posted 5 days ago

Design Verification Lead

Texas Instruments · Bengaluru, Karnataka, India
Oracle
You are 5 days behind. JobBeeper subscribers saw this role while it was still new.

At a glance

The key details from the original listing.

Posted 5 days ago
CompanyTexas Instruments
LocationBengaluru, Karnataka, India
SourceOracle
Listed5 days ago

Your early-applicant advantage

Live timing from JobBeeper.

Live data
0 min from Oracle publishing this role to us finding it
17 min median time from a role going live to a subscriber being told
6 hours subscribers had this role before this page existed
71,353 roles found in the last 24 hours — the newest are not on this site yet
Start your free trial →

About the role

Description supplied by the original job listing.

Change the world. Love your job.
About the Team:
The High-speed Data development team is focused on building state-of-the-art signal conditioning transceivers for Automotive, Industrial, Enterprise and Personal Electronics markets ranging from Ethernet PHY(s), FPD-Link Serdes & USB re-timers. The data rates range from 100Mbps to 40Gbps posing design challenges in high-speed circuit design and digital signal processing to enable data transfer with high fidelity in challenging industrial and automotive environments. These devices need to be competitive in power & area and are being designed in the 65nm and 28nm process nodes.
The FPD product group charter is to develop High-speed SerDes transceivers for Automotive targeting ADAS (Advanced driver-assistance systems) and In-Vehicle-Infotainment applications. These require high-reliability communication links that support auto-driving, and high-resolution graphic applications. The high-speed SerDes designs require significant signal conditioning in Analog with Digital assist to calibrate / adapt the system in challenging electrical environments in the vehicle. The signal chain includes high bandwidth blocks (multi-Ghz) and signal processing data path designs that support multi-Gsps throughput involving clock recovery, channel adaptation, echo cancellation and forward error correction (FEC) to enable highly reliable links. Designed in 28nm CMOS process, the target for these designs is low power and low cost with best-in-industry performance.
Minimum Requirements
B.E/B.Tech or higher
Digital design and modeling knowledge.
Strong Debug skills
5 years of experience
Preferred qualification:
Design knowledge
Soft Skills:
Passion, Self-drive, Hard work, Willingness to learn

Get JobBeeper Mobile App

Never miss a job opening! Get instant job alerts on your phone.

Subscribers see fresh openings within minutes. Download the JobBeeper App on Google Play to get real-time push notifications and apply before anyone else.

⚡ Instant Push Alerts 🎯 Tailored Filters 🚀 Direct Employer Links
GET IT ON Google Play

More openings worth a look

Recently tracked roles with full details and direct application links.

6 roles
Good roles move before most people even see them. Tell JobBeeper what you want and get fresh matches delivered in minutes.
Start your free trial →
⚡ Get fresh job alerts 📱 Get App