RTL Design Verification Engineer

Design Verification Engineer
Company: PQAngels Technologies Pvt. Ltd.
Location: Bengaluru
Experience: 5–11 Years
Employment Type: Full-Time
About PQAngels Technologies :
PQAngels Technologies is a product engineering company operating across the Silicon-to-Software stack. Founded by experienced engineers, we help customers accelerate innovation through Semiconductor, ASIC, VLSI, Embedded, and Product Engineering services.
Job Summary :
We are looking for experienced Design Verification Engineers with strong hands-on expertise in SystemVerilog and UVM to work on ASIC, Subsystem, and SoC-level verification.
The ideal candidate will have experience developing reusable verification environments, creating verification plans and testbenches, executing regressions, debugging failures, driving functional coverage closure, and supporting verification signoff.
Key Responsibilities ;
Develop verification plans, test strategies, and verification methodologies.
Design and develop reusable UVM-based verification environments.
Develop and maintain SystemVerilog/UVM testbenches.
Create test cases and verification scenarios for Subsystem and SoC-level designs.
Perform functional coverage analysis and drive coverage closure.
Develop and implement SystemVerilog Assertions (SVA).
Perform protocol and interface-level verification.
Execute simulations and regression suites.
Debug RTL and verification issues and perform root-cause analysis.
Support verification signoff and closure activities.
Collaborate with Architecture, RTL Design, Physical Design, and Integration teams.
Participate in design and verification reviews.
Prepare verification documentation, reports, and technical specifications.
Participate in technical discussions and customer interactions when required.
Mandatory Technical Skills
Strong hands-on experience in SystemVerilog.
Strong hands-on experience with UVM.
Experience with SystemVerilog Assertions (SVA).
Strong understanding of functional coverage and coverage closure.
Hands-on experience in ASIC / Subsystem / SoC / Functional Verification.
Experience verifying high-speed interfaces and protocols such as:
PCIe
DDR / DDR4 / DDR5 / LPDDR
USB
Ethernet
NoC (Network-on-Chip)
Strong debugging and root-cause analysis skills.
Scripting experience with Python, TCL, or Perl.
Good understanding of ASIC/VLSI design and verification flows.
EDA Tools
Experience with one or more of the following:
Synopsys VCS
Cadence Xcelium
Siemens QuestaSim
Synopsys Verdi
Qualification & Experience
Bachelor's or Master's degree in Electronics, Electrical Engineering, ECE, VLSI, Microelectronics, or a related field.
5–11 years of relevant Design Verification experience.
Preferred Professional Skills
Strong communication and interpersonal skills.
Excellent analytical and problem-solving abilities.
Strong ownership and collaboration skills.
Ability to work effectively with global teams.
Good stakeholder management and customer interaction skills.
Ability to work independently as well as collaboratively.
Why Join PQAngels Technologies ?
Work on advanced semiconductor and ASIC projects.
Gain exposure to Subsystem and SoC-level verification.
Work with experienced semiconductor and VLSI professionals.
Collaborate with global customers and engineering teams.
Opportunity to work on challenging projects across the Silicon-to-Software stack.
Strong opportunities for technical learning and career growth.
If you are an experienced Design Verification Engineer with strong SystemVerilog + UVM expertise and hands-on experience in ASIC, Subsystem, or SoC verification, we would like to hear from you.

Work arrangement
No