Live opening · Posted 4 days ago
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About the role
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Job Requirements
Design and implementation of UVM/SystemVerilog verification environments (checkers, trackers, scoreboards, assertions, functional coverage).
Creation of test plans and test cases to exercise design features and drive code/functional coverage closure.
Running regressions, analyzing failure signatures, debugging issues, and coordinating fixes with design and emulation teams.
Collaboration with system architects and cross-functional teams on feature verification and debug activities.
Verification of interconnect and bus protocol behavior (CHI/AHB/AXI/ACE/ACE-Lite) and related system interactions..
Work arrangement
No
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