Live opening · Posted 3 days ago

Physical Design Engineer

AMISEQ · United States (Remote)
Linkedin Yes
You are 3 days behind. JobBeeper subscribers saw this role while it was still new.

At a glance

The key details from the original listing.

Posted 3 days ago
CompanyAMISEQ
LocationUnited States (Remote)
Salary$65/hr - $70/hr
Work modeYes
SourceLinkedin
Listed3 days ago

Your early-applicant advantage

Live timing from JobBeeper.

Live data
10 min from Linkedin publishing this role to us finding it
10 min median time from a role going live to a subscriber being told
6 hours subscribers had this role before this page existed
66,056 roles found in the last 24 hours — the newest are not on this site yet
Start your free trial →

About the role

Description supplied by the original job listing.

Position: Physical Design Engineer
Location: Remote
Duration: 12 months contract
Job Summary:
We are seeking a highly skilled Physical Design Engineer to drive block-level implementation and optimization activities for advanced ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flow, timing, power, area optimization, and tape-out support.
Key Responsibilities:
Execute block-level physical design implementation from floorplan to tape-out.
Develop and optimize floorplans, macro placement, and power-aware design methodologies.
Perform placement optimization to achieve timing, power, area, and congestion targets.
Drive Clock Tree Synthesis (CTS), routing, and ECO implementation activities.
Support timing analysis, timing closure, and signoff readiness.
Optimize design utilization, congestion, and routability across implementation stages.
Perform DFM-related fixes and support signoff closure requirements.
Collaborate with STA, DFT, and RTL teams to resolve implementation issues.
Support tape-out activities and ensure design quality requirements are met.
Develop automation scripts using TCL, Perl, and Python to improve design productivity.
Required Qualifications:
Strong understanding of ASIC physical design and implementation flow.
Hands-on experience with Synopsys Fusion Compiler.
Experience in floorplanning, placement, CTS, routing, and ECO implementation.
Knowledge of timing analysis fundamentals and timing closure methodologies.
Understanding of congestion management, utilization optimization, and routing concepts.
Familiarity with LEF/DEF, Liberty, Verilog, and standard physical design file formats.
Basic understanding of IR Drop, EM analysis, and Physical Verification flows.
Strong scripting skills in TCL, Perl, and/or Python.
Excellent debugging, problem-solving, and teamwork skills.
Preferred Qualifications:
Experience with advanced technology nodes and full-chip implementation.
Exposure to signoff tools, DFM methodologies, and successful tape-out cycles.

Work arrangement
Yes

Get JobBeeper Mobile App

Never miss a job opening! Get instant job alerts on your phone.

Subscribers see fresh openings within minutes. Download the JobBeeper App on Google Play to get real-time push notifications and apply before anyone else.

⚡ Instant Push Alerts 🎯 Tailored Filters 🚀 Direct Employer Links
GET IT ON Google Play

More openings worth a look

Recently tracked roles with full details and direct application links.

6 roles
Good roles move before most people even see them. Tell JobBeeper what you want and get fresh matches delivered in minutes.
Start your free trial →
⚡ Get fresh job alerts 📱 Get App