Live opening · Posted 4 days ago

Senior ASIC RTL Design Engineer

SmartSoC Solutions Pvt Ltd · Greater Bengaluru Area (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 4 days ago
CompanySmartSoC Solutions Pvt Ltd
LocationGreater Bengaluru Area (On-site)
Work modeNo
SourceLinkedin
Listed4 days ago

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About the role

Description supplied by the original job listing.

SmartSoC, a Virtusa Company, is a leading semiconductor engineering services organization specializing in end-to-end ASIC, SoC, FPGA, Embedded Systems, and VLSI design solutions. Backed by Virtusa's global engineering capabilities, SmartSoC partners with leading semiconductor companies to deliver innovative, high-quality silicon solutions across the entire chip development lifecycle.
We're looking for an experienced RTL Microarchitecture Lead to join our semiconductor team and drive the architecture and design of next-generation SoCs.
Availability: Immediate or currently serving notice candidates is preferred.
📍 Location: Bangalore and Hyderabad
👨 💻 Experience: 5+ Years
Key Responsibilities
Drive SoC microarchitecture from specification to sign-off.
Develop and review microarchitecture documents, including:
Top-level architecture & block diagrams
Clock, Reset & Power Management
SoC Fabrics & Protocol Bridges
Fuse, Boot & Security Architecture
IP Planning & Interfaces
Pinout & Ball Mapping
System & Test Planning
Design Feasibility & PPA Analysis
Develop microarchitecture to meet SoC performance, power, and area (PPA) targets.
Author MAS/PRD documents and lead architecture reviews for IP sign-off.
Deliver RTL, UPF, and timing constraints in collaboration with design teams.
Work closely with SoC, FPGA, DV, DFT, and Physical Design teams through implementation and tape-out.
Review implementation plans and ensure design quality through final sign-off.
Required Skills
Strong expertise in ASIC RTL Design & Microarchitecture
Verilog / VHDL
High-Speed SerDes Protocols (PCIe, USB, Ethernet, LPDDR, ONFI, etc.)
Bus & Interconnect Protocols (AXI, AHB, APB, NoC, IOSF, etc.)
Clock, Reset & Power Management
RTL Development, Lint, UPF & Timing Constraints
SoC Integration & PPA Optimization
Experience with Verification, DFT & Physical Design flows
Version Control Systems (Git/Perforce)
Scripting (TCL, Python, Perl or Shell)
Experience collaborating with Firmware teams
Preferred Profile
Proven experience in architecting and delivering complex SoCs from concept to production.
Strong understanding of RTL implementation, design sign-off, and semiconductor development lifecycle.
Ability to drive cross-functional teams and technical reviews.
🎓 Qualification: B.E./B.Tech./M.E./M.Tech. in Electronics, Electrical Engineering, Computer Science, or a related field.

Work arrangement
No

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