Design Verification Engineer

Company Description PRIMEVLSI PRIVATE LIMITED delivers end-to-end solutions and services in semiconductor, embedded systems, and software development, with a strong focus on evolving technologies. The company applies design thinking and flexible engagement models to address complex and challenging customer needs. PRIMEVLSI is driven by a vision to become a global leader in semiconductor, embedded, and software development services. The organization is recognized in the semiconductor industry for pioneering innovative business models in VLSI design services, offering opportunities to work on cutting-edge projects and methodologies.
Role Description The Design Verification Engineer will work on-site in Bengaluru in a full-time capacity, collaborating closely with design and architecture teams to ensure high-quality semiconductor IP and SoC verification. Day-to-day responsibilities include developing verification plans, creating testbenches, writing test cases, and executing simulations for RTL blocks and subsystems. The role involves performing functional and formal verification, analyzing coverage metrics, identifying corner cases, and driving closure of verification milestones. The engineer will debug complex design and verification issues, document findings, and contribute to continuous improvement of verification methodologies, flows, and automation. This position requires proactive communication with cross-functional teams and adherence to project schedules and quality standards.
Qualifications
Strong knowledge of Functional Verification and Debugging, with experience in creating and executing comprehensive verification test plans.
Hands-on experience in Formal Verification methodologies and tools to validate design correctness and detect corner-case issues.
Proficiency in RTL Design and understanding of hardware description languages (e.g., Verilog, SystemVerilog) for reviewing and analyzing design implementations.
Solid foundation in Computer Architecture, including processors, memory subsystems, and interfaces, to interpret specifications and derive meaningful verification scenarios.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
Familiarity with industry-standard verification environments, simulation tools, and version control systems.
Strong analytical and problem-solving abilities, with attention to detail and a structured approach to debugging.
Effective communication skills and ability to collaborate within multidisciplinary engineering teams.
Experience with UVM or similar verification methodologies, scripting (e.g., Python, Perl, Shell), and exposure to ASIC/SoC design flows is an advantage.

Work arrangement
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