Mixed- Signal Systems and Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Qualifications
New graduates strongly encouraged to apply!
Experience in developing and verifying real-numbered behavioral models in SystemVerilog
Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS
Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc
Working experience in low power Architecture
Working experience in Cadence Virtuoso Schematic Composer and ADE
Experience with Analog Assertion Based Verification
Experience in TB development will be a strong plus
Experience in writing scripts in languages such as Perl or Python
Excellent teammate with excellent communication skills
Experience with FPGA prototyping is a plus Responsibilities
You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation.
As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
Verifying that the behavior models are accurate representations of analog schematics
Integrating the models with RTL
Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions.
DSP experience a huge plus. Documenting modeling and verification results for formal review We’re doing work that matters. Help us solve what others can’t
We’re doing work that matters. Help us solve what others can’t.

Work arrangement
No