Live opening · Posted 2 days ago

Design Verification Engineer | BCP

Texas Instruments · Knoxville, TN, United States
Oracle
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At a glance

The key details from the original listing.

Posted 2 days ago
CompanyTexas Instruments
LocationKnoxville, TN, United States
SourceOracle
Listed2 days ago

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About the role

Description supplied by the original job listing.

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Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Knoxville. In this role, you will develop and execute verification strategies that ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive, and consumer applications.
As a Design Verification Engineer, you will work across the full verification cycle – from developing detailed verification plans and building test benches through running coverage regressions, tracking closure, and contributing to continuous improvements in DV methodology – collaborating closely with digital design and systems engineering teams.
Responsibilities include:
Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon success
Develop test benches, tests, and simulations at RTL and gate-level (GLS) for the entire chip
Run coverage regressions to meet defined coverage goals
Track and communicate verification status, issues, and concerns
Work with regression tools and develop scripts to submit cases for regression analysis
Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods, and flows
Minimum requirements:
Bachelor’s degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, or related field
3+ years of experience in design verification or a related role
Preferred qualifications:
Experience with functional verification methodologies including simulation, assertions, and coverage-driven verification
Proficiency in SystemVerilog and UVM-based testbench development
Experience with Mixed Signal verification a plus
Experience with System Verilog real number models a plus
Familiarity with RTL simulation tools (Cadence Xcelium, Synopsys VCS, or equivalent)
Experience with gate-level simulation and timing-aware verification flows
Scripting skills for regression automation and verification flow development (Python, Tcl, or Perl)
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Demonstrated strong interpersonal, analytical, and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Ability to take the initiative and drive for results

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