Principal Design Verification Engineer — Digital & AMS

About Texas Instruments
At TI, we design and manufacture analog and embedded semiconductors trusted in the world's most critical systems — from automotive and industrial to communications and power management. Our Design Verification team is the backbone of first-pass silicon success, ensuring every product that reaches the market meets the highest bar of functional correctness and quality.
About the Role
We are seeking a Staff Design Verification Engineer — Digital & AMS to serve as a Subject Matter Expert (SME) with a TI-wide charter. This is not a conventional DV role — you will own the verification standard across block to full-chip, lead AMS and digital verification with equal mastery, and serve as TI's trusted technical voice in front of customers and partners.
You will sit at the intersection of deep verification expertise, cross-functional leadership, and an unwavering commitment to first-pass silicon success — making every quality decision that protects every TI product that reaches the market.
What You'll Do
📐 Verification Methodology & Standards
Define and establish TI-wide Design Verification methodologies, flows, and best practices — setting the quality and coverage benchmark that all projects measure against
Architect the verification planning framework TI teams adopt — translating design intent into rigorous test strategies, coverage models, and regression practices
Champion digital verification standards — UVM, constrained random verification, SystemVerilog assertions (SVA), and coverage-driven closure — at block and full-chip level
🔬 AMS Verification Ownership
Own the complete AMS verification landscape — from Verilog-AMS (VAMS) and Real-Number Modeling (RNM) to EENET and behavioral abstraction techniques
Deliver robust co-simulation validation of analog and mixed-signal blocks within digital verification flows
Apply strategic judgment in modeling technique selection — balancing scope, speed, complexity, and accuracy at every stage
✅ Sign-Off Authority & Quality Guardianship
Hold sign-off authority on verification completeness — functional coverage, code coverage, assertions, and regression — your approval the final assurance before any product advances to silicon
Stand as TI's quality guardian, instilling shift-left practices, early bug detection, and design-for-verification thinking from the earliest stages of the design cycle
🤝 Cross-Functional & Customer Engagement
Serve as TI's primary technical representative in customer engagements, design reviews, and partner discussions — communicating verification strategy and quality status with authority
Orchestrate collaboration with Design, EDA, Library, Memory, and IP teams to resolve verification bottlenecks and integrate verification seamlessly into the design flow
Evaluate and qualify EDA tools and verification platforms with data-driven assessments of capability, quality, and productivity
🌱 Mentorship & Community Building
Mentor DV engineers across TI to build a verification community that outlasts any individual project
Champion a culture of quality consciousness that permeates every stage of the design cycle
What You Bring
✅ Experience: 12+ years of hands-on Design Verification experience with equal command of Digital DV and AMS verification
✅ Education: B.S. or M.S. in Electronics Engineering, Electrical Engineering, or VLSI Design
✅ UVM Mastery: Proven command of UVM-based verification — testbench architecture, constrained random stimulus, coverage-driven closure, and regression management
✅ SVA Expertise: Deep proficiency in SystemVerilog and assertion-based verification (SVA) — writing, reviewing, and deploying assertions as a first-class quality instrument
✅ AMS Verification: Demonstrated experience in RNM, VAMS, mixed-signal co-simulation, and behavioral modeling within a digital verification environment
✅ Cadence Toolchain: Proficiency with Xcelium simulation, JasperGold formal verification, and vManager coverage management
✅ Sign-Off Ownership: Established ability to independently own and deliver verification sign-off — from test plan through full functional and coverage closure
✅ Communication: Exceptional written and verbal communication skills with experience presenting to internal stakeholders and external customers
✅ Analytical Aptitude: Ability to dissect complex, multi-dimensional problem statements into well-defined, tractable verification challenges
Bonus Points If You Have
⭐ 12–18 years of progressive DV experience in an SME, methodology lead, or technical architect capacity
⭐ Hands-on depth in formal verification — property checking, connectivity verification, and CDC/RDC analysis
⭐ Exposure to hardware-assisted verification platforms — Cadence Palladium or equivalent — for accelerated simulation of complex mixed-signal SoCs
⭐ Grounding in low-power verification methodologies — UPF-aware simulation, power-intent verification, and multi-voltage domain checking
⭐ Background in mixed-signal or analog-dominant product verticals — automotive, industrial, power management, or communications ICs
⭐ DV flow development and automation — scripting in Python, Tcl, or Perl for regression frameworks and coverage infrastructure
⭐ Track record in customer-facing or pre-silicon collaboration roles — supporting verification readiness reviews and silicon bring-up engagements
⭐ Working knowledge of DFT integration from a verification standpoint — scan insertion, BIST, and boundary scan interaction with the verification environment
Why TI?
🌍 Set verification standards that impact billions of devices worldwide
🔭 Work with cutting-edge EDA tools and world-class semiconductor design teams
🤝 Be the technical authority whose decisions shape TI's silicon quality story
💼 Competitive compensation, comprehensive benefits, and a platform to build your technical legacy

Work arrangement
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