Lead SOC Architect

Own the system architecture that turns Vicharak’s advanced compute technology into a complete, programmable, power-efficient AI accelerator SoC.
THE ROLE
Vicharak is developing a high-performance AI accelerator based on its proprietary compute architecture. We are looking for a Lead SoC Architect to define how compute, memory, interconnect, control, I/O, power management, and software interfaces come together as a production-ready chip.
You will set architectural direction and carry the key decisions through RTL design, verification, physical implementation, software development, tapeout, and silicon bring-up. This is a hands-on technical leadership role working across the compute architecture, RTL, verification, physical design, compiler, firmware, and systems teams.
WHAT YOU WILL OWN
• Own the complete SoC architecture, including the compute subsystem, memory hierarchy, on-chip interconnect, control processors, DMA, I/O, clocking, reset, power management, security, and debug infrastructure.
• Define the integration of Vicharak’s memory macros, including data movement, buffering, scheduling, refresh management, precision support, synchronization, and error handling.
• Architect the interconnect and NoC topology, including bandwidth allocation, latency, arbitration, quality of service, and connectivity between compute, memory, and I/O subsystems.
• Define the memory subsystem, including on-chip SRAM organization, cache or scratchpad architecture, external memory interfaces, address mapping, interleaving, and bandwidth management.
• Translate target AI workloads into requirements for throughput, latency, compute utilization, memory capacity and bandwidth, power, and silicon area.
• Build and maintain performance, bandwidth, and power models for representative neural-network workloads and use the results to guide architecture decisions.
• Define the command, synchronization, interrupt, memory-management, security, debug, and host-communication architecture.
• Select and integrate internal and third-party IP, including processor cores, memory controllers, interface controllers, security blocks, and debug infrastructure.
• Establish the SoC power architecture, including clock domains, power domains, voltage domains, operating states, clock gating, and power gating.
• Partner with physical design and package teams on die size, macro placement, floorplanning, power delivery, thermal constraints, and timing feasibility.
• Work with compiler and software teams to define the programming model, register architecture, runtime behavior, memory model, and performance expectations.
• Author and own architecture specifications and drive reviews to closure across design, verification, physical design, firmware, and software.
• Review microarchitecture specifications, RTL, verification plans, performance results, and implementation reports against the intended architecture.
• Support tapeout, silicon bring-up, performance characterization, and post-silicon debug.
• Mentor engineers and represent SoC architecture in technical discussions with IP vendors, foundries, partners, and customers.
WHAT WE ARE LOOKING FOR
• 15+ years of experience in SoC architecture, accelerator architecture, processor architecture, or complex ASIC development.
• Experience taking at least one complex SoC from architecture definition through tapeout and silicon bring-up.
• Deep understanding of SoC interconnects, NoCs, memory hierarchies, DMA engines, interrupt systems, clocking, reset, and power management.
• Strong understanding of AI accelerator dataflows, tensor operations, quantized arithmetic, memory bandwidth, compute utilization, and data movement.
• Experience converting workload requirements into hardware architecture and measurable performance, power, and area targets.
• Strong knowledge of SRAM-based designs, scratchpad memory, cache architectures, external memory controllers, and system bandwidth modelling.
• Experience integrating internal and third-party IP into a complete SoC.
• Working knowledge of RTL design, functional verification, physical design, DFT, firmware, and silicon validation.
• Understanding of floorplanning, timing closure, power delivery, thermal limits, package constraints, and their architectural impact.
• Ability to make quantitative system-level tradeoffs, document them clearly, and lead technical reviews to closure.
• Bachelor’s, Master’s, or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or an equivalent field.
ESPECIALLY RELEVANT
• Neural processing units, GPUs, DSPs, or other domain-specific accelerators.
• Transformer, CNN, vision, or multimodal inference workloads.
• Low-precision formats such as INT8, INT4, FP8, BF16, or mixed-precision computation.
• RISC-V or other embedded processor-subsystem integration.
• Advanced power management and low-power SoC design.
• Experience with 15nm-class or more advanced process technologies.
APPLY.
Include a short description of the most complex SoC or accelerator architecture you have owned, your personal contribution, the decisions you made, and whether the design reached tapeout and silicon.

Work arrangement
No