Senior Digital IC Design / RTL Engineer

Role Overview:
We are seeking an experienced Digital IC Design Engineer to join our silicon design team. In this role, you will lead the architecture, micro-architecture, RTL design, and integration of digital logic blocks powering our high-performance sensor platforms. You will be responsible for bringing complex control logic, digital signal processing (DSP) pipelines, image processing engines, and low-power control sub-systems from architectural concept through synthesis, physical implementation support, and silicon bring-up.
Key Responsibilities
● RTL Architecture & Design: Architect and implement RTL (SystemVerilog/Verilog) for digital sub-systems, control engines, sensor interface controllers, and signal processing hardware modules.
● DSP & Edge AI Acceleration: Design high-efficiency digital filters, readout pipelines, and hardware accelerators optimized for sensor signal processing and low-power edge compute.
● Low-Power Design Execution: Implement low-power digital design methodologies (clock gating, power gating, multi-voltage domain UPF/CPF flows) to minimize static and dynamic power consumption.
● Timing & Synthesis: Perform logic synthesis, static timing analysis (STA), and equivalence checking; collaborate closely with physical design teams to resolve timing closure, floorplanning, and DFT constraints.
● Design Verification Collaboration: Work with verification engineers to define test plans, write assertions (SVA), coverage monitors, and ensure high functional coverage for tape-out readiness.
● Silicon Bring-Up: Participate in lab validation, post-silicon bring-up, and FPGA prototyping/emulation to verify digital logic performance on hardware.
Qualifications & Requirements:
● Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, VLSI, or a related field.
● Core Expertise:
Strong track record in RTL design using SystemVerilog / Verilog for complex digital or mixed-signal ASICs/SoCs.
Experience with low-power architecture design techniques and UPF/CPF power intent specifications.
Deep understanding of front-end ASIC flows: linting, synthesis (Synopsys Design Compiler), STA (PrimeTime), and CDC/RDC verification.
Experience with standard SoC bus protocols (AMBA AXI/AHB/APB) and common sensor communication interfaces (SPI, I2C, MIPI, UART).
● Silicon Success: Proven experience taking digital blocks through the complete ASIC lifecycle to successful tape-out in deep sub-micron nodes.
● Bonus Qualifications: Experience with image sensor readout digital architectures, DSP filter design, or FPGA prototyping platforms (Xilinx/AMD, Zynq).
What We Offer:
● Collaborative culture working alongside industry veterans in image sensors and system architecture.
● Opportunity to build high-impact, semiconductor technology for critical global applications.
● Competitive compensation package including equity options.
About Bharat Semi (www.bsemis.com)
Bharat Semi is a fabless semiconductor technology company developing high-reliability sensors and semiconductor-based sensing platforms. We bridge the physical-digital interface by building AI-ready hardware engineered for demanding environments spanning defense, surveillance, automotive, and industrial IoT workloads. We push the boundaries of low-power, high-precision chip architecture to power the next generation of intelligent, mission-critical sensing devices.

Work arrangement
Yes