Live opening · Posted 19 hours ago

Digital Design Verification Engineer

Altera · Iași, Romania (Remote)
Workday
You are 19 hours behind. JobBeeper subscribers saw this role while it was still new.

At a glance

The key details from the original listing.

Posted 19 hours ago
CompanyAltera
LocationIași, Romania (Remote)
SourceWorkday
Listed19 hours ago

Your early-applicant advantage

Live timing from JobBeeper.

Live data
8 min from Workday publishing this role to us finding it
17 min median time from a role going live to a subscriber being told
6 hours subscribers had this role before this page existed
70,831 roles found in the last 24 hours — the newest are not on this site yet
Start your free trial →

About the role

Description supplied by the original job listing.

Job Details:
Job Description:
Altera is the world's largest independent, pure-play FPGA company. Our programmable logic devices power data centers, telecommunications infrastructure, AI accelerators, and industrial systems. Recently spun out from Intel as an independent company, we combine decades of FPGA heritage with the focus and agility of a fresh start.
We're looking for a talented, self-motivated engineer to join our Design Verification team. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification.
This role is ideal for an early-career engineer who wants to build deep technical expertise in high-speed silicon verification. You'll work alongside experienced engineers on real silicon shipping to production, with plenty of opportunity to learn, grow, and take ownership as you ramp up.
What We Build
Our team develops and verifies high-speed SerDes IP — the physical layer technology that moves data across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters: the world's data moves through what we build.
What You'll Do
Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks
Write testbenches, functional coverage models, and assertions
Run simulations, analyze failures, and debug both RTL and testbench issues
Collaborate with design, architecture, and analog teams on block-level and top-level verification.
Qualifications:
BSc in Electrical Engineering, Computer Engineering, or equivalent
0–5 years of experience in digital design or verification (internships, academic projects, or industry)
Working knowledge of SystemVerilog and basic familiarity with UVM concepts
Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing
Strong analytical and debug mindset — you enjoy getting to the bottom of a problem
Good communication skills in English (spoken and written)
Candidates should preferably be able to reside in Iași.
Job Type: Regular
Shift:Shift 1 (Romania)
Primary Location:Iași, Romania (Remote)
Additional Locations:
Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Get JobBeeper Mobile App

Never miss a job opening! Get instant job alerts on your phone.

Subscribers see fresh openings within minutes. Download the JobBeeper App on Google Play to get real-time push notifications and apply before anyone else.

⚡ Instant Push Alerts 🎯 Tailored Filters 🚀 Direct Employer Links
GET IT ON Google Play

More openings worth a look

Recently tracked roles with full details and direct application links.

6 roles
Good roles move before most people even see them. Tell JobBeeper what you want and get fresh matches delivered in minutes.
Start your free trial →
⚡ Get fresh job alerts 📱 Get App