Live opening · Posted 6 hours ago

Multiple Post Silicon Electrical Validation Engineer roles (grades T2 to T5) at Cadence Bangalore

Cadence Design Systems · Bengaluru, Karnataka, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 6 hours ago
CompanyCadence Design Systems
LocationBengaluru, Karnataka, India (On-site)
Work modeNo
SkillsPython, C++
SourceLinkedin
Listed6 hours ago

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About the role

Description supplied by the original job listing.

There are multiple openings for Post Silicon Electrical Validation Engineer roles (grades T2 to T5, ie, Test Engineer II to Senior Principal Test Engineer/Senior Test Engineering Manager) in High Speed SERDES Physical Layer Electrical Validation Domain at Cadence Design Systems, Bangalore. The roles are intended for candidates with direct experience in this domain in the range 2 years to 15 years (depending upon the job grade targeted)
Why choose Cadence Design Systems? These roles offer the opportunity to work on the post silicon electrical validation of various cutting edge high speed SERDES and Die to Die designs. Apart from the challenging work and opportunity for gain deep knowledge in these technologies, Cadence also offers attractive compensation packages.
What we are looking for in potential candidates is listed below.
Minimum Qualifications:
• BTECH/MTECH in in an Electronics stream with experience between 2-15 years (depending upon the job grade targeted) in Post-Silicon Physical Layer Electrical Validation
• Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc
• Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etcPreferred Qualifications:
• Experience managing small teams (at least 2 members and above) is a strong plus for T4 grade and above roles
• Experience leading the complete post silicon validation efforts for at least one full project is a strong plus for T4 grade and above roles
• 1-2 years of experience in Analog, PLL,FPGA Design, PCB schematic and layout design & Prototyping is a strong plus
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
• Experience conducting hiring interviews and mentoring new hires
• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.

Work arrangement
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