Technical Lead I - VLSI

Role Description
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .
Summary
UST is looking for an RTL Design Lead with experience in PCIe Gen5/6
The Opportunity
We are looking for a Lead RTL Design Engineer to drive the architecture, design, and execution of high-performance digital subsystems with a strong focus on PCIe-based designs. This role requires deep expertise in RTL development, protocol understanding, and end-to-end ownership from architecture to validation.
Key Responsibilities
Own end-to-end RTL design and micro-architecture for PCIe-based subsystems
Translate system requirements into scalable architecture and RTL implementation
Design PCIe datapath, control logic, buffering, flow control, and ordering mechanisms
Develop synthesizable RTL using Verilog
Lead synthesis, lint, CDC/RDC, timing analysis and closure
Drive FPGA/ASIC integration, bring-up, and validation
Debug PCIe protocol and system-level issues
Collaborate with verification, validation, and firmware teams
Lead design reviews, code reviews, and technical sign-offs
Mentor team members and guide technical execution.
Required Qualifications
8-12 years of RTL design experience (FPGA/ASIC)
Strong expertise in Verilog
Strong digital design fundamentals (FSMs, FIFOs, pipelines, clock/reset)
Deep understanding of PCIe protocol (TLPs, LTSSM, flow control, ordering)
Experience with FPGA tools (Vivado/Quartus)
Strong experience in synthesis, timing closure, CDC, lint, and debug
Strong debugging skills across simulation and hardware
Experience with high-speed interfaces (PCIe, DDR)
Preferred Qualifications
Familiarity with AXI/APB/AHB, I2C, SPI, UART
FPGA board bring-up and lab debugging experience
Scripting knowledge (Python/Tcl/Shell)
Experience with protocol analysis tools
Leadership Expectations
Drive architecture-first design thinking
Anticipate PCIe corner cases and design for robustness
Improve debug cycle time through better design practices
Influence cross-team decisions and technical direction
What We Believe
We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.
Humility
We will listen, learn, be empathetic and help selflessly in our interactions with everyone.
Humanity
Through business, we will better the lives of those less fortunate than ourselves.
Integrity
We honour our commitments and act with responsibility in all our relationships.
Equal Employment Opportunity Statement
UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.
All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.
UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.
To support and promote the values of UST.
Comply with all Company policies and procedures
Skills
SystemVerilog, Verilog, ASIC, RTL Design

Work arrangement
No