Live opening · Posted 7 days ago
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About the role
Description supplied by the original job listing.
Location:- Bangalore/Hyderabad
NP:- Immediate-30 Days
JD for Intel PD
6-10 years experience in Physical Design implementation
Responsible to independently handle the execution and delivery of a medium to complex full chip/blocks RTL2GDS implementation
Experience in PPA analysis and improvement strategies and excellent debugging skills
Played a significant role in multiple tape-outs across technology nodes
Skill Set (all or most of the below list)
Full chip/complex block implementation
IO planning (package i/f, ESD, Multi Voltage), ESD
Partitioning , Hierarchical flows
Power estimation, planning and analysis (static and dynamic IR, EM)
Floor planning, placement & congestion, timing closure, CTS, post CTS flow
PV: DRC/LVS/ GDS checks
Schedule recovery, team mentoring, customer interaction
Exposure/knowledge on Synthesis/STA/DFT/LEC/VCLP
Proficient in industry standard EDA tool flows (SNPS & CDN)
Low power implementation, verification.
TCL Scripting knowledge
Experience on Intel lower nodes like18A is desired.
Work arrangement
No
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