Principal FW/SW Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Engineer – Embedded Firmware & Software
Location: Toronto or Ottawa, Ontario (Remote)
Travel: Occasional travel to Astera Labs’ San Jose headquarters, approximately twice per year, for chip bring-up and project coordination
Employment: Full-time
Role Overview
Join Astera Labs’ Signal Connectivity Engineering team as a Principal Engineer shaping the firmware and software that makes advanced connectivity products adaptive, reliable, and production-ready. You will own embedded software across analog connectivity and Ethernet retimer platforms, from low-level hardware abstraction and calibration through link management, diagnostics, validation, and customer deployment.
This is a high-impact role at the intersection of embedded systems, mixed-signal hardware, and Ethernet physical-layer behavior. You will work across architecture, lab debug, automation, and customer integration while partnering with silicon, analog, systems, validation, and applications teams. Your work will help deliver purpose-built connectivity for rack-scale AI infrastructure as Astera Labs continues to scale.
Key Responsibilities
Firmware Architecture & Product Ownership
Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs.
Design firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry.
Architect control algorithms, state machines, and tuning flows that manage analog and high-speed interfaces across process, voltage, and temperature variation.
Define software quality gates, validation criteria, and release practices from pre-silicon planning through production deployment.
Ethernet, Lab Debug & System Integration
Debug firmware behavior across Ethernet configurations, link states, and failure modes by tracing interactions among Layer 1 PHY, SERDES, FEC/PCS, MAC, retimer, and gearbox components.