Senior Design Verification Engineer

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.
We are seeking a Senior Design Verification Engineer (5–7 years of experience) to join our Data Center Connectivity DV team. This role is ideal for engineers passionate about building verification environments from the ground up, performing functional and power-aware simulations, and integrating VIPs for standard protocols such as MAC, PHY, and AXI. The position involves CPUSS integration, verification of cutting-edge technologies.
Key Responsibilities
Take ownership oftest-bench development usingUVM for Subsystem and SoC.
Translate test bench architecture specifications into detailed DV tasks and build verification environments from scratch.
Develop key test bench components including agents, scoreboards for data integrity checks, pass/fail criteria, protocol assertions, and functional coverage points
Set up UVM register model generation using register description files and industry-standard automation tools (e.g.,Autogen).
Automate C-based register programming API generation from register description files through scripting.
Perform complete address map and register verification using UVM Register methodology.
Verify all features comprehensively, including standalone test cases, concurrent traffic, use-case scenarios, and corner cases.
Debug regression failures, perform root cause analysis, and collaborate closely with designers to resolve issues
Perform comprehensive power-aware verification across all voltage corners, validating power and sub-power domains along with retention strategies.
Set up and execute gate-level simulations, including a dedicated test suite for GLS that covers system boot and main data-path functionality
Required Skills And Experience
Education: B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, or Computer Engineering.
Experience: 5–7 years of strong hands-on DV development and integration experience in SoC, networking, or interconnect logic.
Proficiency in System Verilog and UVM coding for verification. Knowledge of C language.
Experience with ARM or RISC-V CPU subsystems.
Solid understanding of connectivity and interconnect protocols such as AMBA (AXI/AHB/APB); familiarity with PCIe or Ethernet is a plus.
Knowledge of clock/reset architectures, FIFOs, CDC, and low-power verification techniques.
Strong debugging and problem-solving skills; experience with Git flow.
Hands-on experience with simulation tools (e.g.,VCS, Questa).
Strong knowledge of UPF (Unified Power Format), level shifter implementation, and power management strategies for low-power design.
Why This Role
Work on next-gen data center connectivity.
Gain deep exposure toDV architecture,UVM based TB development, E2E SoC development cycle and post-silicon bring-up.
Be part of a highly technical team that values innovation, ownership, and learning.
Competitive compensation, technical growth, and exposure to cutting-edge design challenges.

Work arrangement
No