Live opening · Posted 4 days ago

Hiring ODC - Lead Design Verification Engineers - Hyderabad

Mirafra Technologies · Hyderabad, Telangana, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 4 days ago
CompanyMirafra Technologies
LocationHyderabad, Telangana, India (On-site)
Work modeNo
SourceLinkedin
ListedPosted 4 days ago

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About the role

Description supplied by the original job listing.

Company Description Mirafra Technologies is a leading provider of Turnkey ASIC solutions and semiconductor engineering services, supporting global technology companies from concept to silicon to system. With a team of over 2,200 engineers and delivery centers across India, the United States, Germany, Taiwan, and Malaysia, Mirafra combines deep domain expertise with a robust global delivery model. The company offers end-to-end capabilities across the semiconductor lifecycle, including architecture, design, verification, physical implementation, embedded software, and system solutions. Mirafra’s track record includes more than 650 tape-out contributions and partnerships with over 50 semiconductor customers, from startups to major technology leaders. In addition, Mirafra helps customers build intelligent embedded products and drive digital transformation through AI, cloud, data engineering, and scalable software solutions.
Role Description
Familiarity with SoCs and boot flow would be useful.
• SV UVM based TB environment setup, usage of UVM VIPs.
• Developing UVM sequences, tests, TB bring up and sanity regressions.
• Familiarity with Software development flow including assembly and C is beneficial.
• Knowledge of system-level architecture including buses like AXI/CHI/ACE5, bridges, memory controllers such as DDR5/LPDDR5/DDR4/LPDDR4
• Knowledge of one or more protocols; PCIe, USB, Ethernet
• Sound knowledge on UPF and power domain crossing
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi
• Strong expertise in DFT-DV verification, like Scan clear / Mem clear / JTAG / IJTAG / Memory repair, Scan dump, ATPG etc…

Work arrangement
No

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