Layout Engineer

Experience 3-8 Years
Location : Bangalore
Position : Memory layout Engineer
Role:
Layout Design of SRAM/CAM/RF custom/compiler memories in TSMC A14/2FF/3FF technologies or Samsung SS8/SS2 technologies.
Responsibilities:
Develop key building blocks of memory architecture, such as Row Decoder, IO, and Control.
Skilled in pitched layout concepts and floor planning for Placement, Power, and Global Routing.
Knowledge of EM/IR requirements.
Compiler-level integration and final verification of Compiler/Custom memories.
Strong knowledge of CMOS fabrication processes, foundries, and challenges in the latest technology nodes.
Skills & Qualifications:
Proficient in industry-standard EDA tools such as Cadence Virtuoso and Mentor Graphics Calibre.
Strong problem-solving, logical reasoning, and communication skills.
Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.
Extensive experience with physical verification tools such as Calibre and ICV (DRC, LVS, ERC, Antenna, and Softcheck Errors).
Proficiency in floor planning, hierarchy layout, and chip integration.
Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
Strong knowledge of memory layout topology; experience with memory compilers is preferred.
Interested candidates can share their updated resumes to shobhna.yadav@smartsocs.com

Work arrangement
No