Live opening · Posted 4 days ago

ASIC RTL Design Lead

eInfochips (An Arrow Company) · Noida, Uttar Pradesh, India (On-site)
Linkedin No
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At a glance

The key details from the original listing.

Posted 4 days ago
CompanyeInfochips (An Arrow Company)
LocationNoida, Uttar Pradesh, India (On-site)
Work modeNo
SourceLinkedin
ListedPosted 4 days ago

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About the role

Description supplied by the original job listing.

ASIC Design Lead (Senior & Mid-Level) | ASIC / SoC Development
Location: Noida, India
Experience: 6+ Years
Employment Type: Full-Time
About the Role
We are seeking highly motivated ASIC Design Leads to contribute to next-generation silicon development programs. In this role, you will work across architecture definition, RTL development, and implementation, enabling high-performance and power-efficient ASIC/SoC designs.
You will collaborate closely with architecture, verification, and physical design teams to deliver production-quality silicon from specification through tape-out.
Role 1: ASIC Design Engineer/Lead (6+ Years Experience)
Responsibilities
Define and drive digital design architecture for complex SoC and ASIC subsystems
Translate micro-architecture specifications into scalable and high-quality RTL implementations
Refine functional requirements throughout the design lifecycle in collaboration with cross-functional teams
Implement low-power design methodologies aligned with system-level goals
Perform synthesis, timing closure, and design optimization
Drive design quality through CDC analysis, constraint development, and sign-off readiness
Partner with verification and physical design teams to ensure successful integration and tape-out
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related discipline
6+ years of experience in digital ASIC/SoC design
Strong expertise in RTL design using SystemVerilog/Verilog
Hands-on experience in ASIC synthesis, timing analysis, and CDC methodologies
Working knowledge of P&R flows and low-power design using UPF
Deep understanding of end-to-end digital design and implementation flow
Preferred Qualifications
Experience owning complex IP or subsystem delivery
Exposure to advanced node designs and power optimization techniques
Strong debugging and design closure experience across multiple tape-outs
Why Join Us
Work on cutting-edge semiconductor technologies and complex silicon programs
Collaborate with globally distributed engineering teams
Opportunity to influence architecture and product innovation
Culture focused on technical excellence, ownership, and continuous learning

Work arrangement
No

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