CXL IP Validation Lead

Job Title
CXL IP Validation Lead
Location: Bangalore, Karnataka, India
Experience
8–12 Years
Industry
Semiconductor | Telecom | Networking | Product Engineering
Notice Period : Preferred Immediate joiners.
🚀 Hiring: CXL IP Validation Lead
About the Role
We are seeking an experienced and highly technical CXL IP Validation Engineer to join our silicon IP validation team. In this role, you will own the end-to-end post-silicon validation of next-generation Compute Express Link (CXL) controller and subsystem IPs. You will architect test scenarios, drive coverage closure, and ensure seamless integration of CXL with other high-speed interfaces.
Key Responsibilities
Test Planning & Architecture: Define validation strategies, author detailed test plans, and help execute them
Protocol Verification: Focus heavily on verifying CXL protocols (CXL.io, CXL.cache, CXL.mem), as well as PCI Express (PCIe) Gen6/5.
Testing & Coverage: Create directed and constrained-random tests, run regressions, and achieve functional and performance tests.
Mentorship: Lead, guide, and mentor junior verification engineers to accelerate their growth and ensure right-first-time delivery.
Compliance & Interoperability: Ensures the IP passes strict PCI-SIG and CXL Consortium compliance workshops using standard exercisers and analyzers (e.g., Teledyne LeCroy) to verify link layer training and state machines.
Basic Qualifications
Education: Bachelor’s (B.E./B.Tech) or Master’s (M.S./M.Tech) degree in Electrical Engineering, Electronics, or Computer Science.
Experience: 8 to 12 years of hands-on experience in post-silicon IP/SoC validation, with specific focus on high-speed interfaces.
Deep understanding of micro-architecture for complex SOCs
Required Technical Skills
Protocol Expertise: Deep understanding of PCIe, CXL, or UCIe protocols.
Scripting: Good working knowledge of Python, Perl, or Tcl for automation.
Email :: kolakaluri.saritha@capgemini.com/nikhil.shrirang-jadhav@capgemini.com

Work arrangement
Hybrid