Hardware Engineering Internship 2027

Hardware Engineering Internship 2027
Cambridge, UK | Full-time | Fixed-term, 10–12 weeks | Hybrid
Salary: £30,000–£35,000 per annum, depending on experience, paid pro rata for the internship duration.
About us
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
Our full-time summer internships give current students in technical fields the opportunity to apply their skills and expertise in an industrial setting.
You will join us at our head office in Cambridge, UK, for 10 to 12 weeks, working alongside talented software and hardware engineers, mathematicians, quantum information theorists and physicists who are experts in their fields.
You will have a dedicated supervisor and work on a project designed to make the best use of your existing skills while developing your knowledge of quantum computing and quantum error correction. We will support you in producing a meaningful piece of work that you can be proud of by the end of your internship.
Previous interns have committed code to industry-standard open-source compilers, co-authored research papers and led the design of new software tools.
What you will do
Collaborate with experienced hardware and software engineers to investigate and evaluate architectural optimisations
Enhance the decoder’s architecture to improve its flexibility and processing speed
Explore different design approaches and evaluate their potential benefits
Contribute to design decisions involving space and time trade-offs, balancing functionality, resource use and performance
Communicate your work clearly through technical discussions, presentations and written documentation
Develop your understanding of FPGA development, quantum computing and quantum error correction
What we need
You must be a current student at the time of application, either:
In the second or a later year of a Bachelor’s degree
Partway through a Master’s degree
Partway through a PhD