Senior Test Engineer

Location: Ipoh, Perak
Our Team:
Our Product and Test Engineering team develops the test solutions that qualify every product Semtech ships, working across the full portfolio — optical interconnect, protection, sensing, power and wireless. Supporting multiple business lines means unusual technical range: the characterization problem for a 1.6T optical driver looks nothing like the one for a MEMS force sensor, and you'll see both. Within the Asia Hub, our team spans Taiwan, Malaysia, and Vietnam, supporting LoRa, SIP, AMW/FHS, and ISC products from first silicon bring-up through high-volume manufacturing.
Job Summary:
We are seeking an experienced Senior Test Engineer to support our test development and optimization activities. The Senior Test Engineer will work closely with the test engineering team to develop test solutions, analyze test data, and contribute to improving test efficiency and coverage.
Responsibilities:
Lead the development and debug of test programs for product validation and characterization
Perform in-depth data analysis of test results to identify failure modes, trends, and opportunities for test optimization
Own test hardware setup, maintenance, and troubleshooting of automated test equipment (ATE)
Document test procedures, specifications, and create technical reports on test coverage and correlation studies
Drive test time reduction initiatives and continuous improvements while maintaining test quality and reliability
Minimum Qualifications:
Bachelor's degree in Electronics & Electrical Engineering, Computer Engineering, or related field
5+ years of experience in test engineering within the semiconductor industry
Strong programming skills in C/C++, Python, or other relevant languages
Proficiency with ATE platforms such as Advantest V93K and/or Teradyne UltraFLEX/FLEX is desirable
Deep understanding of ATE test methodologies including digital, mixed-signal, and parametric testing
Desired Qualifications
Hands-on expertise with Advantest V93K and/or Teradyne UltraFLEX/FLEX in wafer-level (CP) and/or final test (FT) environments
Proven experience in probe card and load board design, hardware bring-up, and correlation studies
Strong statistical background including PAT, SBL, SYL, GR&R, and yield improvement techniques
Demonstrated ability to mentor junior engineers and drive best practices across multi-site teams